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JPH0338917A Expired / Lapsed JP ⏱️ 0.0 years remaining

Inverter circuit

Assignee: NEC Corp
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Filing: 1989-07-05
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Granted: —
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Expires: 2009-07-05
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Abstract

Abstract PURPOSE:To suppress sudden turning on/off of a transistor(TR) while a switch is in a transient state and to reduce the generation of noise by inserting a back gate control TR between a back gate and a power terminal of a P-channel TR and an N-channel TR to shift the back gate voltage from a reference voltage. CONSTITUTION:The drain and the source of a 2nd P-channel TR QP2 and N- channel TR QN2 for back gate control are inserted respectively between a back gate terminal BGP and a power terminal TD of a 1st P-channel TR QP1 and between a back gate terminal BGN, and a power terminal TS of a 1st N-channel TR QN1 in an inverter circuit of a CMOS IC. Then a back gate power supply 1 connecting each gate to a common gate G is added. Then the 1st TRs QP1 and QN1 are not suddenly turned on at the transient time of rise and fall, the waveform of an output voltage VD is relaxed and no noise is generated.

Inventors

  • 👤 Hiroko Tanaka
  • 👤 裕子 田中

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 18:39
CPC Classifications
—

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