US5852375A
Expired / Lapsed
US
⏱️ 0.0 years remaining
5v tolerant I/O circuit
Assignee: SILICON SYSTEMS RESEARCH Ltd
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Filing: 1997-02-07
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Granted: 1998-12-22
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Expires: 2017-02-07
Abstract
Abstract An integrated circuit has an I/O circuit that is connected to an I/O PAD. The I/O PAD may have greater voltage than the VDD associated with the integrated circuit so there is provided a switching circuit that is connected between the VDD and the I/O PAD. An output circuit is also provided that comprises n-channel transistors connected between the PAD and the ground. There is a cascode arrangement of p-channel transistors connected between the I/O PAD and VDD.
Inventors
- 👤 Timothy Gerard Byrne
- 👤 Brian T. Morley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:11
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
108 words
An I/O circuit comprising: an I/O PAD connected to receive a first voltage; a first circuit having at least one first type transistor connected between a second voltage and the I/O PAD and a second circuit having at least one second type transistor connected between the I/O PAD and a third voltage; and a cascode arrangement of at least first and second transistors of the first type of transistors between the I/O PAD and the third voltage and a junction between a source of the first transistor and a drain of the second transistor being connected to a gate of the at least one second type of transistor.
Claim 2
Dependent Claim
108 words
An I/O circuit comprising: an I/O PAD connected to receive a first voltage; a first circuit having at least one first type transistor connected between a second voltage and the I/O PAD and a second circuit having at least one second type transistor connected between the I/O PAD and a third voltage; and a cascode arrangement of at least first and second transistors of the first type of transistors between the I/O PAD and the third voltage and a junction between a source of the first transistor and a drain of the second transistor being connected to a gate of the at least one second type of transistor.
Claim 3
Dependent Claim
41 words
The I/O circuit according to claim 1 further comprising: a third transistor connected in series between the at least one second type transistor and the third voltage and, a gate control circuit operatively connected to a gate of the third transistor.
Claim 4
Dependent Claim
28 words
The I/O circuit according to claim 1 wherein each transistor of the cascode arrangement includes a drain and a gate with the gate being connected to the drain.
Claim 5
Dependent Claim
48 words
The I/O circuit according to claim 3 wherein the cascode arrangement is a potential divider and the location of the junction of the first and second transistors being a first tap and selected to divide the first voltage to an intermediate voltage approximately equal to the second voltage.
Claim 6
Dependent Claim
24 words
The I/O circuit according to claim 4 wherein the intermediate voltage is applied to the gate of the at least one second type transistor.
Claim 7
Dependent Claim
63 words
The I/O circuit according to claim 5 wherein the potential divider further includes at least a third transistor of the first type between a drain of the first transistor and the third voltage and a junction between the drain of the first transistor and a source of the third transistor being connected to a gate of the at least one first type transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-21 | 2002-06-22 | 2002-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-21 | 2006-06-22 | 2006-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-21 | 2010-06-22 | 2010-12-22 | $7700.00 | Window Closed / Lapsed |