Method and structure for high capacitance memory cells

Claim 2

A memory cell, comprising: a lateral transistor formed in a layer of semiconductor material outwardly from a substrate, the transistor including a first source/drain region, a body region and a second source/drain region; a trench capacitor formed in a trench and coupled to the second source/drain region; and wherein the trench capacitor includes a polycrystalline semiconductor plate formed in the trench that is coupled to the second source/drain region, a second plate formed by the substrate with a textured surface of the substrate including an array of silicon asperities, wherein silicon asperities within the array of silicon asperities have an average center to center spacing of 20 nanometers (nm), and an insulator layer that separates the polycrystalline semiconductor plate from the array of silicon asperities.

Claim 3

The memory cell of claim 1 , wherein the polycrystalline semiconductor plate comprises polysilicon.

Claim 4

The memory cell of claim 1 , wherein the second plate comprises a heavily doped p-type silicon substrate.

Claim 5

The memory cell of claim 1 , wherein each silicon asperity in the array of silicon asperities has an average height of 100 nm.

Claim 6

The memory cell of claim 1 , wherein each silicon asperity in the array of silicon asperities has an average diameter of 10 nm.

Claim 7

A memory cell, comprising: a vertical transistor formed outwardly from a substrate, the transistor including a first source/drain region, a body region and a second source/drain region that are vertically aligned; wherein a surface of the second source/drain region includes an array of silicon asperities, wherein silicon asperities within the array of silicon asperities have an average center to center spacing of 20 nanometers (nm); and a trench capacitor with a polycrystalline semiconductor plate that is formed in a trench that surrounds the array of silicon asperities on the surface of the second source/drain region of the transistor.

Claim 8

A memory cell, comprising: a vertical transistor formed outwardly from a substrate, the transistor including a first source/drain region, a body region and a second source/drain region that are vertically aligned; wherein a surface of the second source/drain region includes an array of silicon asperities, wherein silicon asperities within the array of silicon asperities have an average center to center spacing of 20 nanometers (nm); and a trench capacitor with a polycrystalline semiconductor plate that is formed in a trench that surrounds the array of silicon asperities on the surface of the second source/drain region of the transistor.

Claim 9

The memory cell of claim 6 , wherein the second source/drain region comprises single crystalline silicon, and wherein the array of silicon asperities is formed by dry etching the surface of the second source/drain region in the presence of a sulfur hexafluoride (SF 6 ) gas.

Claim 10

The memory cell of claim 6 , wherein the polycrystalline semiconductor plate comprises polysilicon.

Claim 11

The memory cell of claim 6 , wherein each silicon asperities in the array of silicon asperities has an average height of 100 nm.

Claim 12

The memory cell of claim 6 , wherein each silicon asperities in the array of silicon asperities has an average diameter of 10 mn.

Claim 13

A memory device, comprising: an array of memory cells, each memory cell including an access transistor that is coupled to a trench capacitor, wherein a first plate of the trench capacitor includes a surface having an array of silicon asperities, wherein silicon asperities within the array of silicon asperities have an average center to center spacing of 20 nanometers (nm), and a second plate of the trench capacitor is disposed adjacent to the first plate; a number of bit lines that are each selectively coupled to a number of the memory cells at a first source/drain region of the access transistor; a number of word lines disposed substantially orthogonal to the bit lines and coupled to gates of a number of access transistors; and a row decoder coupled to the word lines and a column decoder coupled to the bit lines so as to selectively access the cells of the array.

Claim 14

A memory device, comprising: an array of memory cells, each memory cell including an access transistor that is coupled to a trench capacitor, wherein a first plate of the trench capacitor includes a surface having an array of silicon asperities, wherein silicon asperities within the array of silicon asperities have an average center to center spacing of 20 nanometers (nm), and a second plate of the trench capacitor is disposed adjacent to the first plate; a number of bit lines that are each selectively coupled to a number of the memory cells at a first source/drain region of the access transistor; a number of word lines disposed substantially orthogonal to the bit lines and coupled to gates of a number of access transistors; and a row decoder coupled to the word lines and a column decoder coupled to the bit lines so as to selectively access the cells of the array.

Claim 15

The memory device of claim 11 , wherein the first plate comprises a single crystalline silicon source/drain region, wherein the array of silicon asperities is formed using a self-structured mask and by dry etching the surface in the presence of a sulfur hexafluoride (SF 6 ) gas.

Claim 16

The memory cell of claim 11 , wherein the second plate comprises polysilicon.

Claim 17

The memory device of claim 11 , wherein each silicon asperities in the array of silicon asperities has an average height of 100 nm.

Claim 18

The memory device of claim 11 , wherein each silicon asperities in the array of silicon asperities has an average diameter of 10 nm.

Claim 19

The memory device of claim 13 , wherein the access transistor comprises a lateral transistor that is coupled to the second plate of the trench capacitor, wherein the first plate comprises a single crystalline silicon substrate, wherein the array of silicon asperities is formed on a surface of the substrate using a self-structured mask and by dry etching the surface in the presence of a sulfur hexafluoride (SF 6 ) gas.

Claim 20

A memory device, comprising: an array of memory cells, each memory cell including an access transistor that is coupled to a trench capacitor, wherein a first plate of the trench capacitor includes a textured surface having a plurality of asperities formed thereon, wherein the asperities within the plurality of asperities have an average center to center spacing of 20 nanometers (nm), wherein a second plate of the trench capacitor is disposed adjacent to the first plate, wherein the second plate of the trench capacitor also includes a textured surface having an array of asperities; a number of bit lines that are each selectively coupled to a number of the memory cells at a first source/drain region of the access transistor; a number of word lines disposed substantially orthogonal to the bit lines and coupled to gates of a number of access transistors; and a row decoder coupled to the word lines and a column decoder coupled to the bit lines so as to selectively access the cells of the array comprises a lateral transistor.

Claim 21

A memory device, comprising: an array of memory cells, each memory cell including an access transistor that is coupled to a trench capacitor, wherein a first plate of the trench capacitor includes a textured surface having a plurality of asperities formed thereon, wherein the asperities within the plurality of asperities have an average center to center spacing of 20 nanometers (nm), wherein a second plate of the trench capacitor is disposed adjacent to the first plate, wherein the second plate of the trench capacitor also includes a textured surface having an array of asperities; a number of bit lines that are each selectively coupled to a number of the memory cells at a first source/drain region of the access transistor; a number of word lines disposed substantially orthogonal to the bit lines and coupled to gates of a number of access transistors; and a row decoder coupled to the word lines and a column decoder coupled to the bit lines so as to selectively access the cells of the array comprises a lateral transistor.

Claim 22

The memory device of claim 17 , wherein each asperity on the first plate and on the second plate has an average height of 100 nm.

Claim 23

The memory device of claim 17 , wherein each asperity on the first plate and the second plate has an average diameter of 10 nm.

Claim 24

The memory device of claim 17 , wherein the access transistor in each memory cell comprises a lateral transistor.

Claim 25

A memory cell, comprising: a transistor formed in a layer of semiconductor material outwardly from a substrate, the transistor including a first source/drain region, a body region and a second source/drain region; a trench capacitor formed in a trench and coupled to the second source/drain region; and wherein the trench capacitor includes a polycrystalline semiconductor plate formed in the trench that is coupled to the second source/drain region, a second plate formed by side surfaces of the trench capacitor, the side surfaces extending outwardly from a bottom surface of the trench capacitor, the side surfaces including a textured surface having an array of silicon asperities, and an insulator layer that separates the polycrystalline semiconductor plate from the array of silicon asperities, wherein the silicon asperities within the array of silicon asperities have an average center to center spacing of 20 nanometers (nm).

Claim 26

A memory cell, comprising: a transistor formed in a layer of semiconductor material outwardly from a substrate, the transistor including a first source/drain region, a body region and a second source/drain region; a trench capacitor formed in a trench and coupled to the second source/drain region; and wherein the trench capacitor includes a polycrystalline semiconductor plate formed in the trench that is coupled to the second source/drain region, a second plate formed by side surfaces of the trench capacitor, the side surfaces extending outwardly from a bottom surface of the trench capacitor, the side surfaces including a textured surface having an array of silicon asperities, and an insulator layer that separates the polycrystalline semiconductor plate from the array of silicon asperities, wherein the silicon asperities within the array of silicon asperities have an average center to center spacing of 20 nanometers (nm).

Claim 27

The memory cell of claim 21 , wherein the bottom surface is free of asperities.

Claim 28

The memory cell of claim 21 , wherein the bottom surface is formed by a substrate.

Claim 29

The memory cell of claim 21 , wherein the side surfaces are formed by a substrate.

Claim 30

The memory cell of claim 21 , wherein the array of silicon asperities are uniform on the side surfaces.

Claim 31

A memory cell, comprising: a transistor formed in a layer of semiconductor material outwardly from a substrate, the transistor including a first source/drain region, a body region and a second source/drain region; a trench capacitor formed in a trench and coupled to the second source/drain region; and wherein the trench capacitor includes a polycrystalline semiconductor plate formed in the trench that is coupled to the second source/drain region, a second plate formed by side surfaces of the trench capacitor, the side surfaces extending outwardly from a bottom surface of the trench capacitor, the side surfaces including a textured surface having an array of silicon asperities, and an insulator layer that separates the polycrystalline semiconductor plate from the array of silicon asperities, wherein the array of silicon asperities has a density of approximately 10 12 pillars per square centimeter.

Claim 32

A memory cell, comprising: a transistor formed in a layer of semiconductor material outwardly from a substrate, the transistor including a first source/drain region, a body region and a second source/drain region; a trench capacitor formed in a trench and coupled to the second source/drain region; and wherein the trench capacitor includes a polycrystalline semiconductor plate formed in the trench that is coupled to the second source/drain region, a second plate formed by side surfaces of the trench capacitor, the side surfaces extending outwardly from a bottom surface of the trench capacitor, the side surfaces including a textured surface having an array of silicon asperities, and an insulator layer that separates the polycrystalline semiconductor plate from the array of silicon asperities, wherein the array of silicon asperities has a density of approximately 10 12 pillars per square centimeter.

Claim 33

A memory cell, comprising: a transistor formed in a layer of semiconductor material outwardly from a substrate, the transistor including a first source/drain region, a body region and a second source/drain region; a trench capacitor formed in a trench and coupled to the second source/drain region; and wherein the trench capacitor includes a polycrystalline semiconductor plate formed in the trench that is coupled to the second source/drain region, a second plate formed by side surfaces of the trench capacitor, the side surfaces extending outwardly from a bottom surface of the trench capacitor, the side surfaces including a textured surface having an array of silicon asperities, and an insulator layer that separates the polycrystalline semiconductor plate from the array of silicon asperities, wherein the array of silicon asperities are spaced approximately 18 nm from adjacent silicon asperities.

Claim 34

A memory cell, comprising: a transistor formed in a layer of semiconductor material outwardly from a substrate, the transistor including a first source/drain region, a body region and a second source/drain region; a trench capacitor formed in a trench and coupled to the second source/drain region; and wherein the trench capacitor includes a polycrystalline semiconductor plate formed in the trench that is coupled to the second source/drain region, a second plate formed by side surfaces of the trench capacitor, the side surfaces extending outwardly from a bottom surface of the trench capacitor, the side surfaces including a textured surface having an array of silicon asperities, and an insulator layer that separates the polycrystalline semiconductor plate from the array of silicon asperities, wherein the array of silicon asperities are spaced approximately 18 nm from adjacent silicon asperities.

Claim 35

A trench capacitor, comprising: a polycrystalline semiconductor plate in a trench; a second plate formed by side surfaces of the trench, the side surfaces extending outwardly from a bottom surface of the trench capacitor, the side surfaces including a textured surface having an array of silicon asperities; and an insulator layer that separates the polycrystalline semiconductor plate from the array of silicon asperities, wherein silicon asperities within the array of silicon asperities have an average center to center spacing of 20 nanometers (nm).

Claim 36

A trench capacitor, comprising: a polycrystalline semiconductor plate in a trench; a second plate formed by side surfaces of the trench, the side surfaces extending outwardly from a bottom surface of the trench capacitor, the side surfaces including a textured surface having an array of silicon asperities; and an insulator layer that separates the polycrystalline semiconductor plate from the array of silicon asperities, wherein silicon asperities within the array of silicon asperities have an average center to center spacing of 20 nanometers (nm).

Claim 37

The capacitor of claim 28 , wherein the bottom surface is free of asperities.

Claim 38

The capacitor of claim 28 , wherein the bottom surface is formed by a substrate.

Claim 39

The capacitor of claim 28 , wherein the side surfaces are formed by a substrate.

Claim 40

The capacitor of claim 28 , wherein the array of silicon asperities has a density of approximately 10 12 pillars per square centimeter.

Claim 41

The capacitor of claim 28 , wherein the array of silicon asperities are uniform on the side surfaces.

Claim 42

The capacitor of claim 28 , wherein the array of silicon asperities are spaced approximately 18 nm from adjacent silicon asperities.