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US6490224B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Delay-locked loop with binary-coupled capacitor

Assignee: Mosaid Technologies Inc
•
Filing: 2001-07-16
•
Granted: 2002-12-03
•
Expires: 2021-07-16
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Abstract

Abstract A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.

Inventors

  • 👤 Troy A. Manning

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 08:23
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 124 words
A method of locking a delay-locked loop to an input clock signal, comprising the steps of: providing a digital count; producing a pulse in response to an edge of the input clock signal; delaying the pulse with a delay circuit having a delay time corresponding to the digital count to produce a feedback clock signal; comparing the feedback clock signal to the input clock signal; producing a signal indicative of the feedback clock signal leading or lagging the input clock signal; if the feedback clock signal leads the input clock signal, changing the digital count in a first direction; and if the feedback clock signal lags the input clock signal, changing the digital count in a second direction that is opposite the first direction.
Claim 2
Independent Claim 124 words
A method of locking a delay-locked loop to an input clock signal, comprising the steps of: providing a digital count; producing a pulse in response to an edge of the input clock signal; delaying the pulse with a delay circuit having a delay time corresponding to the digital count to produce a feedback clock signal; comparing the feedback clock signal to the input clock signal; producing a signal indicative of the feedback clock signal leading or lagging the input clock signal; if the feedback clock signal leads the input clock signal, changing the digital count in a first direction; and if the feedback clock signal lags the input clock signal, changing the digital count in a second direction that is opposite the first direction.
Claim 3
Dependent Claim 40 words
The method of claim 1 , wherein the act of changing the digital count in the first direction comprises increasing the digital count and wherein the act of changing the digital count in the second direction comprises decreasing digital count.
Claim 4
Dependent Claim 69 words
The method of claim 1 , wherein the act of delaying the pulse with a delay circuit comprises: charging a capacitance to a selected voltage; controllably changing the charge of the capacitance in response to the pulse; detecting when the voltage to which the capacitance is charged passes a threshold voltage; and producing a delayed pulse in response to the voltage to which the capacitance passing the threshold voltage.
Claim 5
Dependent Claim 39 words
The method of claim 3 wherein the act of delaying the pulse with a delay circuit having a delay time corresponding to the digital count comprises changing the magnitude of the capacitance as a function of the digital count.
Claim 6
Dependent Claim 93 words
The method of claim 1 wherein the act of producing a signal indicative of the feedback signal leading or lagging the input clock signal comprises: applying the feedback signal to a first switch; applying the input clock signal to a second switch; if the feedback clock signal passes through the first switch, opening the second switch; if the input clock signal passes through the second switch, opening the first switch; detecting if the feedback clock signal passes through the first switch; and detecting if the input clock signal passes through the second switch.
Claim 7
Dependent Claim 28 words
The method of claim 5 , further comprising disabling the incrementing or decrementing of the digital count if both of the clock signals pass through the respective switches.
Claim 8
Dependent Claim 14 words
The method of claim 1 wherein the digital count comprises a binary digital count.
Claim 9
Dependent Claim 12 words
The method of claim 1 wherein the count comprises a binary count.
Claim 10
Independent Claim 104 words
A method of locking a delay-locked loop to an input clock signal, comprising the steps of: delaying the input clock signal by a delay time corresponing to a count to produce a feedback clock signal; comparing the feedback clock signal to the input clock signal; producing a signal indicative of the feedback clock signal leading or lagging the input clock signal; if the feedback clock signal leads the input clock signal, changing the digital count in a first direction; and if the feedback clock signal lags the input clock signal, changing the digital count in a second direction that is opposite the first direction.
Claim 11
Independent Claim 104 words
A method of locking a delay-locked loop to an input clock signal, comprising the steps of: delaying the input clock signal by a delay time corresponing to a count to produce a feedback clock signal; comparing the feedback clock signal to the input clock signal; producing a signal indicative of the feedback clock signal leading or lagging the input clock signal; if the feedback clock signal leads the input clock signal, changing the digital count in a first direction; and if the feedback clock signal lags the input clock signal, changing the digital count in a second direction that is opposite the first direction.
Claim 12
Dependent Claim 36 words
The method of claim 9 wherein the act of changing the count in the first direction comprises increasing the count and wherein the act of changing the count in the second direction comprises decreasing the count.
Claim 13
Dependent Claim 71 words
The method of claim 9 wherein the act of delaying the input clock signal comprises: charging a capacitance to a selected voltage; controllably changing the charge of the capacitance in response to a transition of the input clock signal; detecting when the voltage to which the capacitance is charged passes a threshold voltage; and producing a delayed pulse in response to the voltage to which the capacitance passing the threshold voltage.
Claim 14
Dependent Claim 35 words
The method of claim 11 wherein the act of delaying the input clock signal by a delay time corresponding to the count comprises changing the magnitude of the capacitance as a function of the count.
Claim 15
Dependent Claim 93 words
The method of claim 9 wherein the act of producing a signal indicative of the feedback signal leading or lagging the input clock signal comprises: applying the feedback signal to a first switch; applying the input clock signal to a second switch; if the feedback clock signal passes through the first switch, opening the second switch; if the input clock signal passes through the second switch, opening the first switch; detecting if the feedback clock signal passes through the first switch; and detecting if the input clock signal passes through the second switch.
Claim 16
Dependent Claim 27 words
The method of claim 13 , further comprising disabling the incrementing or decrementing of the count if both of the clock signals pass through the respective switches.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2005-12-02 2006-06-03 2006-12-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2009-12-02 2010-06-03 2010-12-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2013-12-02 2014-06-03 2014-12-03 $7700.00 Window Closed / Lapsed

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