US6476434B1
Expired / Lapsed
US
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4 F2 folded bit line dram cell structure having buried bit and word lines
Assignee: Micron Technology Inc
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Filing: 2000-05-16
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Granted: 2002-11-05
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Expires: 2020-05-16
Abstract
Abstract A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells, and a pair of word lines are located in each of the isolation trenches. The word lines are oriented vertically widthwise in the trench and are adapted to gate alternate access transistors, so that both an active and a passing word line can be contained within each memory cell to provide a folded bit line architecture. The memory cell has a surface area that is approximately 4 F 2 , where F is a minimum feature size. Also disclosed are processes for fabricating the DRAM cell using bulk silicon or a silicon on insulator processing techniques.
Inventors
- 👤 Wendell P. Noble
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:18
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/34; H10B12/01; H10B12/02; H10B12/05; H10B12/053
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
220 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; a single access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; and a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide on only one side of the vertical structure, wherein the wordline has a side facing the vertical channel which has a vertical length of less than 60 nanometers; and a second word line electrically isolated from the access transistor extending along a. generally vertical sidewall portion of the access transistor opposite the vertical channel region, wherein the bit line and the word lines are located below the active silicon surface of the memory cell structure.
Claim 2
Dependent Claim
220 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; a single access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; and a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide on only one side of the vertical structure, wherein the wordline has a side facing the vertical channel which has a vertical length of less than 60 nanometers; and a second word line electrically isolated from the access transistor extending along a. generally vertical sidewall portion of the access transistor opposite the vertical channel region, wherein the bit line and the word lines are located below the active silicon surface of the memory cell structure.
Claim 3
Dependent Claim
31 words
The memory cell structure according to claim 1 , wherein the word line has a horizontal length which is greater than the vertical length of the side facing the vertical channel.
Claim 4
Dependent Claim
238 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; a single access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide, wherein the word line is oriented horizontally along the sidewall portion of the access transistor; a second word line electrically isolated from the access transistor extending along a generally vertical sidewall portion of the access transistor opposite the vertical channel region, wherein the bit line and the word lines are located below the active silicon surface of the memory cell structure; and a layer of a dielectric material interposed between the bit line and the substrate for electrically isolating the bit line, and the access transistor fabricated on the bit line, from the substrate.
Claim 5
Dependent Claim
238 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; a single access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide, wherein the word line is oriented horizontally along the sidewall portion of the access transistor; a second word line electrically isolated from the access transistor extending along a generally vertical sidewall portion of the access transistor opposite the vertical channel region, wherein the bit line and the word lines are located below the active silicon surface of the memory cell structure; and a layer of a dielectric material interposed between the bit line and the substrate for electrically isolating the bit line, and the access transistor fabricated on the bit line, from the substrate.
Claim 6
Dependent Claim
37 words
The semiconductor memory cell structure of claim 3 , wherein the horizontally oriented word line has a vertical edge opposing the vertical channel, and wherein the vertical edge has a vertical height of less than 60 nanometers.
Claim 7
Dependent Claim
251 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; a single access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide, wherein the wordline has a side with a vertical length of less than 60 nanometers facing the vertical channel; a second word line electrically isolated from the access transistor extending along a generally vertical sidewall portion of the access transistor opposite the vertical channel region, wherein the bit line and the word lines are located below the active silicon surface of the memory cell structure; wherein the word line is oriented horizontally along the sidewall portion of the access transistor; and wherein the surface area of the memory cell structure is approximately 4F 2 , where F is a minimum feature size of the memory cell structure.
Claim 8
Dependent Claim
251 words
A semiconductor memory cell structure fabricated on a substrate of a semiconductor material, the memory cell comprising: a bit line on the substrate; a single access transistor fabricated as a vertical structure on a portion of the bit line, the access transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the access transistor having an upper surface defining an upper active silicon surface for the memory cell structure; a gate oxide formed on the sidewall portion of the access transistor overlying the channel region of the access transistor; a word line extending along the sidewall portion of the access transistor, with a portion of the word line being formed on the gate oxide, wherein the wordline has a side with a vertical length of less than 60 nanometers facing the vertical channel; a second word line electrically isolated from the access transistor extending along a generally vertical sidewall portion of the access transistor opposite the vertical channel region, wherein the bit line and the word lines are located below the active silicon surface of the memory cell structure; wherein the word line is oriented horizontally along the sidewall portion of the access transistor; and wherein the surface area of the memory cell structure is approximately 4F 2 , where F is a minimum feature size of the memory cell structure.
Claim 9
Dependent Claim
31 words
The semiconductor memory cell structure of claim 5 , wherein the word line has a horizontal length which is greater than the vertical length of the side facing the vertical channel.
Claim 10
Dependent Claim
363 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including a single access transistor formed as a vertical structure having first and second source/drain regions and a channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line being at approximately equal vertical position and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell.
Claim 11
Dependent Claim
363 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including a single access transistor formed as a vertical structure having first and second source/drain regions and a channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line being at approximately equal vertical position and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell.
Claim 12
Dependent Claim
40 words
The memory array of claim 7 , wherein the first and second word lines have a horizontal length which is greater than the vertical length of the side facing the channel regions of the first and the fourth access transistors.
Claim 13
Dependent Claim
377 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, including a second isolation trench extending orthogonally to the first-mentioned isolation trench, the second isolation trench containing a dielectric material for providing isolation between the first and second bit lines, and between the first and third access transistors, and between the second and fourth transistors.
Claim 14
Dependent Claim
377 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, including a second isolation trench extending orthogonally to the first-mentioned isolation trench, the second isolation trench containing a dielectric material for providing isolation between the first and second bit lines, and between the first and third access transistors, and between the second and fourth transistors.
Claim 15
Dependent Claim
370 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line.
Claim 16
Dependent Claim
370 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line.
Claim 17
Dependent Claim
368 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, wherein the first bit line functions as the first source/drain region for the first and second access transistors, and the second bit line functions as the first source/drain region for the third and fourth access transistors.
Claim 18
Dependent Claim
368 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, wherein the first bit line functions as the first source/drain region for the first and second access transistors, and the second bit line functions as the first source/drain region for the third and fourth access transistors.
Claim 19
Dependent Claim
428 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, including a gate oxide layer formed on a sidewall of the first access transistor and interposed between the first word line and the channel region of the first access transistor, a gate oxide layer formed on a sidewall of the fourth access transistor and interposed between the second word line and the channel region of the fourth access transistor, and a layer of a dielectric material interposed between the channel region of the second access transistor and the first word line and between the channel region of the third access transistor and the second word line.
Claim 20
Dependent Claim
428 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, including a gate oxide layer formed on a sidewall of the first access transistor and interposed between the first word line and the channel region of the first access transistor, a gate oxide layer formed on a sidewall of the fourth access transistor and interposed between the second word line and the channel region of the fourth access transistor, and a layer of a dielectric material interposed between the channel region of the second access transistor and the first word line and between the channel region of the third access transistor and the second word line.
Claim 21
Dependent Claim
365 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, including a layer of a dielectric material interposed between the bit lines and the substrate for electrically isolating the bit lines, and the access transistors formed on the bit lines, from the substrate.
Claim 22
Dependent Claim
365 words
A memory array fabricated on a semiconductor substrate, the memory array comprising: a plurality of bit lines on the substrate; a plurality of word lines; a plurality of memory cells, each of the memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and at least one isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; at first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried within the dielectric material in the isolation trench and located below an active silicon surface of the memory cell, including a layer of a dielectric material interposed between the bit lines and the substrate for electrically isolating the bit lines, and the access transistors formed on the bit lines, from the substrate.
Claim 23
Dependent Claim
233 words
A folded bit line semiconductor memory array fabricated on a semiconductor substrate, the memory array comprising: at least first and second bit lines on the substrate, the first and second bit lines each having a width F which corresponds to a minimum feature size for the semiconductor memory array; at least first and second access transistors formed on each of the bit lines, each of the access transistors being formed as a vertical structure to have first and second source/drain regions and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the length and the width of each access transistor corresponding to the minimum feature size F; a dielectrically lined trench extending orthogonally to the bit lines between the first and second access transistors on the first and second bit lines; a gate oxide overlying the channel region of the first access transistor on the first and second bit lines; and first and second word lines in each trench, the word lines being oriented horizontally in the trench, the first and second word lines being electrically coupled to the channel region of respective ones of the first access transistors on the first and second bit lines and being electrically isolated from the channel region of respective ones of the second access transistors on the first and second bit lines.
Claim 24
Dependent Claim
233 words
A folded bit line semiconductor memory array fabricated on a semiconductor substrate, the memory array comprising: at least first and second bit lines on the substrate, the first and second bit lines each having a width F which corresponds to a minimum feature size for the semiconductor memory array; at least first and second access transistors formed on each of the bit lines, each of the access transistors being formed as a vertical structure to have first and second source/drain regions and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, the length and the width of each access transistor corresponding to the minimum feature size F; a dielectrically lined trench extending orthogonally to the bit lines between the first and second access transistors on the first and second bit lines; a gate oxide overlying the channel region of the first access transistor on the first and second bit lines; and first and second word lines in each trench, the word lines being oriented horizontally in the trench, the first and second word lines being electrically coupled to the channel region of respective ones of the first access transistors on the first and second bit lines and being electrically isolated from the channel region of respective ones of the second access transistors on the first and second bit lines.
Claim 25
Dependent Claim
39 words
The folded bit line semiconductor memory array of claim 14 , wherein the horizontally oriented word lines have a vertical edge opposing the channel regions, and wherein the vertical edge has a vertical height of less than 60 nanometers.
Claim 26
Dependent Claim
372 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including a single access transistor formed as a vertical structure having first and second source/drain regions and a channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line being at approximately equal vertical position and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors.
Claim 27
Dependent Claim
372 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including a single access transistor formed as a vertical structure having first and second source/drain regions and a channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the access transistor, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line being at approximately equal vertical position and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors.
Claim 28
Dependent Claim
24 words
The semiconductor memory device of claim 16 , wherein each memory cell includes a stacked capacitor on the upper surface of the access transistor.
Claim 29
Dependent Claim
41 words
The semiconductor memory device of claim 16 , including a layer of a dielectric material interposed between the bit lines and the substrate for electrically isolating the bit lines, and the access transistors formed on the bit lines, from the substrate.
Claim 30
Dependent Claim
41 words
The semiconductor memory device of claim 16 , wherein the first and second word lines have a horizontal length which is greater than the vertical length of the side facing the channel regions of the first and the fourth access transistors.
Claim 31
Dependent Claim
379 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line.
Claim 32
Dependent Claim
379 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line.
Claim 33
Dependent Claim
415 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line, wherein the first bit line functions as the first source/drain region for the first and second access transistors and the second bit line functions as the first source/drain region for the third and fourth access transistors.
Claim 34
Dependent Claim
415 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line, wherein the first bit line functions as the first source/drain region for the first and second access transistors and the second bit line functions as the first source/drain region for the third and fourth access transistors.
Claim 35
Dependent Claim
475 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line, including a gate oxide layer formed on a sidewall of the first access transistor and interposed between the first word line and the channel region of the first access transistor, a gate oxide layer formed on a sidewall of the fourth access transistor and interposed between the second word line and the channel region of the fourth access transistor, and a layer of a dielectric material interposed between the channel region of the second access transistor and the first word line and between the channel region of the third access transistor and the second word line.
Claim 36
Dependent Claim
475 words
A semiconductor memory device comprising: a memory array fabricated on a semiconductor substrate and including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells; memory array access circuitry for accessing the memory cells; each of said memory cells including an access transistor having first and second source/drain regions and a channel region, first and second ones of the access transistors each being formed on a first one of the bit lines, and third and fourth ones of the access transistors each being formed on a second one of the bit lines; and an isolation trench extending orthogonally to the first and second bit lines, the isolation trench including a dielectric material for providing isolation between the first and second access transistors and for providing isolation between the third and fourth access transistors; a first one of the word lines extending within the isolation trench in the proximity of the first and third access transistors, the first word line being electrically coupled to the channel region of the first access transistor, wherein the first word line has a side with a vertical length of less than 60 nanometers facing the channel region, and the first word line being electrically isolated from the channel region of the third access transistor; and a second one of the word lines extending within the isolation trench in parallel with the first word line and spaced apart from the first word line, the second word line extending in the proximity of the second and fourth access transistors, the second word line being electrically isolated from the channel region of the second access transistor and being electrically coupled to the channel region of the fourth access transistor, wherein the second word line has a side with a vertical length of less than 60 nanometers facing the channel region of the fourth access transistor, and the first and second word lines being buried in the dielectric material in the isolation trench and located below an active silicon surface of the access transistors, wherein the first and second access transistors each are formed as a vertical structure on the first bit line, and the third and fourth access transistors each are formed as a vertical structure on the second bit line, including a gate oxide layer formed on a sidewall of the first access transistor and interposed between the first word line and the channel region of the first access transistor, a gate oxide layer formed on a sidewall of the fourth access transistor and interposed between the second word line and the channel region of the fourth access transistor, and a layer of a dielectric material interposed between the channel region of the second access transistor and the first word line and between the channel region of the third access transistor and the second word line.
Claim 37
Dependent Claim
212 words
A vertically oriented transistor cell structure fabricated on a substrate of a semiconductor material, the transistor cell comprising: a bit line on the substrate; a single transistor fabricated as a vertical structure on a portion of the bit line, the transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the transistor, the transistor having an upper surface defining an upper active silicon surface for the cell structure; a gate oxide formed on the sidewall portion of the transistor overlying the vertical channel region of the transistor; a gate line extending along the sidewall portion of the transistor, with a portion of the gate line being formed on the gate oxide on only one side of the vertical structure, wherein the gate line has a side facing the vertical channel which has a vertical length of less than 60 nanometers; and a second gate line electrically isolated from the transistor extending along a generally vertical sidewall portion of the transistor opposite the vertical channel region, wherein the bit line and the gate lines are located below the active silicon surface of the memory cell structure.
Claim 38
Dependent Claim
212 words
A vertically oriented transistor cell structure fabricated on a substrate of a semiconductor material, the transistor cell comprising: a bit line on the substrate; a single transistor fabricated as a vertical structure on a portion of the bit line, the transistor having a first source/drain region defined by said bit line portion, a second source/drain region, and a vertical channel region located in a generally vertical sidewall portion on only one side of the vertical structure of the transistor, the transistor having an upper surface defining an upper active silicon surface for the cell structure; a gate oxide formed on the sidewall portion of the transistor overlying the vertical channel region of the transistor; a gate line extending along the sidewall portion of the transistor, with a portion of the gate line being formed on the gate oxide on only one side of the vertical structure, wherein the gate line has a side facing the vertical channel which has a vertical length of less than 60 nanometers; and a second gate line electrically isolated from the transistor extending along a generally vertical sidewall portion of the transistor opposite the vertical channel region, wherein the bit line and the gate lines are located below the active silicon surface of the memory cell structure.
Claim 39
Dependent Claim
23 words
The vertically oriented transistor cell structure of claim 23 , wherein the vertically oriented transistor cell structure is used in a logic circuit.
Claim 40
Dependent Claim
23 words
The vertically oriented transistor cell structure of claim 23 , wherein the vertically oriented transistor cell structure is used in an analog circuit.
Claim 41
Dependent Claim
30 words
The vertically oriented transistor cell structure of claim 23 , wherein the vertically oriented transistor cell structure is adapted for use in a RF and in a mixed mode circuit.
Claim 42
Dependent Claim
32 words
The vertically oriented transistor cell structure of claim 23 , wherein the gate line has a horizontal length which is greater than the vertical length of the side facing the vertical channel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-04 | 2006-05-06 | 2006-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-04 | 2010-05-06 | 2010-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-04 | 2014-05-06 | 2014-11-05 | $7700.00 | Window Closed / Lapsed |