US6040210A
Expired / Lapsed
US
⏱️ 0.0 years remaining
2F-square memory cell for gigabit memory applications
Assignee: Samsung Electronics Co Ltd
•
Filing: 1998-01-26
•
Granted: 2000-03-21
•
Expires: 2018-01-26
Abstract
Abstract A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size.
Inventors
- 👤 Stuart Mcallister Burns, Jr.
- 👤 Hussein Ibrahim Hanafi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:48
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/34; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383; H10B12/05; H10B12/053; H10B12/31; H10B12/39; H10B12/395; H10B12/50; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B69/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
76 words
A method of forming a 2F-square memory device comprising the steps of: forming on a substrate an array of pillars arranged in rows and columns; forming lower doped regions extending inwardly from each sidewall of said pillar, said lower doped regions being separated from each other; forming first and second gate regions on pillar sidewalls, said first and second gate regions being opposite each other along said columns; and forming upper doped regions on said pillars.
Claim 2
Independent Claim
76 words
A method of forming a 2F-square memory device comprising the steps of: forming on a substrate an array of pillars arranged in rows and columns; forming lower doped regions extending inwardly from each sidewall of said pillar, said lower doped regions being separated from each other; forming first and second gate regions on pillar sidewalls, said first and second gate regions being opposite each other along said columns; and forming upper doped regions on said pillars.
Claim 3
Dependent Claim
17 words
The method of claim 1 further comprising forming an insulating layer between said pillars along said rows.
Claim 4
Dependent Claim
21 words
The method of claim 1, wherein the gate regions forming step forms two continuous wordlines per pillars located along said rows.
Claim 5
Dependent Claim
17 words
The method of claim 1, wherein the lower doped regions forming step forms bitlines along said columns.
Claim 6
Dependent Claim
77 words
The method of claim 1, wherein the array forming step includes the steps of: forming column mask lines over said substrate parallel to said columns; etching exposed portions of said substrate to form column trenches; covering said semiconductor device with a second mask; patterning said second mask to form row mask lines over said substrate parallel to said rows; and etching exposed portions of said substrate not covered by said row mask lines to form row trenches.
Claim 7
Dependent Claim
70 words
The method of claim 1, wherein the lower doped regions forming step includes the steps of: forming lower region outdiffusion material in lower portions of column trenches formed in said substrate parallel to said columns; etching said column trenches to separate said outdiffusion material between adjacent columns of pillars and form bitline straps parallel to said columns; and outdiffusing material from said bitline straps to form said lower doped regions.
Claim 8
Dependent Claim
58 words
The method of claim 1, wherein said gate regions forming step includes the steps of: forming column trenches; etching row trenches orthogonal to said column trenches; forming an oxide barrier at bottoms of said row trenches; forming a first gate oxide on sidewalls of said row trenches; and forming a first gate electrode over said first gate oxide.
Claim 9
Dependent Claim
43 words
The method of claim 7 further including the steps of: forming a second gate oxide on said first gate electrode, said first gate electrode being insulated to form a floating gate; and forming a second gate electrode formed over said second gate oxide.
Claim 10
Dependent Claim
21 words
The method of claim 7, wherein the row trenches forming steps forms holes in said row trenches separated by oxide walls.
Claim 11
Dependent Claim
16 words
The method of claim 7 further including forming a stack capacitor over each of said pillars.
Claim 12
Dependent Claim
28 words
The method of claim 7 further including forming a trench capacitor around each of said pillars in trenches separating said pillars and being arranged in rows and columns.
References Cited (Backward Citations)
US4716548A
Cited
US5017977A
Cited
US4774556A
Cited
US4796228A
Cited
US4929988A
Cited
US5001526A
Cited
US4979004A
Cited
US5016067A
Cited
US5016068A
Cited
US5006909A
Cited
US5278090A
Cited
US4964080A
Cited
US5071782A
Cited
US5078498A
Cited
US5146426A
Cited
US5330927A
Cited
US5258634A
Cited
US5338953A
Cited
US5350937A
Cited
US5467305A
Cited
US5386132A
Cited
US5382540A
Cited
US5574299A
Cited
US5432739A
Cited
US5497017A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-21 | 2003-09-20 | 2004-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-21 | 2007-09-20 | 2008-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-21 | 2011-09-20 | 2012-03-21 | $7700.00 | Window Closed / Lapsed |