Method for manufacturing a dynamic RAM having 3-dimensional memory cell structure

Claim 1

A method for manufacturing semiconductor memory devices comprising the steps of: forming a first semiconductor layer of a first conductivity type on a substrate; forming a second semiconductor layer of a second conductivity type on said first semiconductor layer; forming a first insulation film on said second semiconductor layer; forming a third semiconductor layer on said first insulation film; patterning said third semiconductor layer into a column configuration; subjecting a surface of said third semiconductor layer thus patterned to an oxidizing process to form a first oxide film; selectively removing portions of said third semiconductor layer, first insulation film, second semiconductor layer, first semiconductor layer, and substrate by using said first oxide film as a mask to form said first semiconductor layer into a column configuration and form said second semiconductor layer into an annual configuration; removing said first oxide film; forming cut-away portions in a direction of an extension of word lines at portions of said second semiconductor layer which is formed in the annular configuration; forming a second insulation film around said first semiconductor layer which is formed in the column configuration; forming a fourth semiconductor layer on a first resultant structure; etching back said fourth semiconductor layer until said second semiconductor layer is entirely exposed and leaving said fourth semiconductor layer around said second insulation film; forming a third insulation film around said second semiconductor layer which is exposed and said fourth semiconductor layer which is exposed; forming a first conductive layer acting as a word line on a second resultant structure; leaving said first conductive layer on a side wall of said third insulation film; etching back a remaining portion of said first conductive layer to expose a part of said second semiconductor layer; forming an impurity region of the first conductivity type in an area near the exposed portion of said second semiconductor layer; forming a fourth insulation film on a third resultant structure; etching back said fourth insulation film at least until said impurity region of the first conductivity type is exposed; and forming a second conductive layer acting as a bit line in contact with said impurity region of the first conductivity type.

Claim 2

A method for manufacturing semiconductor memory devices comprising the steps of: forming a first semiconductor layer of a first conductivity type on a substrate; forming a second semiconductor layer of a second conductivity type on said first semiconductor layer; forming a first insulation film on said second semiconductor layer; forming a third semiconductor layer on said first insulation film; patterning said third semiconductor layer into a column configuration; subjecting a surface of said third semiconductor layer thus patterned to an oxidizing process to form a first oxide film; selectively removing portions of said third semiconductor layer, first insulation film, second semiconductor layer, first semiconductor layer, and substrate by using said first oxide film as a mask to form said first semiconductor layer into a column configuration and form said second semiconductor layer into an annual configuration; removing said first oxide film; forming cut-away portions in a direction of an extension of word lines at portions of said second semiconductor layer which is formed in the annular configuration; forming a second insulation film around said first semiconductor layer which is formed in the column configuration; forming a fourth semiconductor layer on a first resultant structure; etching back said fourth semiconductor layer until said second semiconductor layer is entirely exposed and leaving said fourth semiconductor layer around said second insulation film; forming a third insulation film around said second semiconductor layer which is exposed and said fourth semiconductor layer which is exposed; forming a first conductive layer acting as a word line on a second resultant structure; leaving said first conductive layer on a side wall of said third insulation film; etching back a remaining portion of said first conductive layer to expose a part of said second semiconductor layer; forming an impurity region of the first conductivity type in an area near the exposed portion of said second semiconductor layer; forming a fourth insulation film on a third resultant structure; etching back said fourth insulation film at least until said impurity region of the first conductivity type is exposed; and forming a second conductive layer acting as a bit line in contact with said impurity region of the first conductivity type.