US6350635B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell having a vertical transistor with buried source/drain and dual gates
Assignee: Micron Technology Inc
•
Filing: 1998-08-24
•
Granted: 2002-02-26
•
Expires: 2018-08-24
Abstract
Abstract An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F 2 , where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.
Inventors
- 👤 Wendell P. Noble
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:33
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/053; H10B12/30; H10B12/48; H10B12/488
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
238 words
A method of forming an integrated circuit, the method comprising: forming a first layer on a substrate, the first layer having a first conductivity type; forming a second layer on the first layer, the second layer having a second conductivity type; forming a third layer on the second layer, the third layer having the first conductivity type; forming a first plurality of substantially parallel trenches extending through the third layer, the second layer, the first layer, and extending at least partially into the substrate, the first plurality of trenches defining a plurality of semiconductor bars; removing an amount of the substrate sufficient to at least partially undercut the plurality of semiconductor bars; forming a first insulating layer between the substrate and the plurality of semiconductor bars, the insulating layer underlying the plurality of semiconductor bars; forming a second plurality of substantially parallel row trenches substantially orthogonally to the first plurality of trenches, the second plurality of substantially parallel row trenches extending through the third layer, the second layer, and extending partially through the first layer such that the first layer serves as a plurality of bit lines; forming a second insulating layer substantially covering a surface of the second plurality of trenches; forming conductors in the second plurality of trenches, each conductor comprising a conductive layer and being disposed in one of the second plurality of trenches; and coupling the bit lines and the conductors to addressing circuitry.
Claim 2
Independent Claim
238 words
A method of forming an integrated circuit, the method comprising: forming a first layer on a substrate, the first layer having a first conductivity type; forming a second layer on the first layer, the second layer having a second conductivity type; forming a third layer on the second layer, the third layer having the first conductivity type; forming a first plurality of substantially parallel trenches extending through the third layer, the second layer, the first layer, and extending at least partially into the substrate, the first plurality of trenches defining a plurality of semiconductor bars; removing an amount of the substrate sufficient to at least partially undercut the plurality of semiconductor bars; forming a first insulating layer between the substrate and the plurality of semiconductor bars, the insulating layer underlying the plurality of semiconductor bars; forming a second plurality of substantially parallel row trenches substantially orthogonally to the first plurality of trenches, the second plurality of substantially parallel row trenches extending through the third layer, the second layer, and extending partially through the first layer such that the first layer serves as a plurality of bit lines; forming a second insulating layer substantially covering a surface of the second plurality of trenches; forming conductors in the second plurality of trenches, each conductor comprising a conductive layer and being disposed in one of the second plurality of trenches; and coupling the bit lines and the conductors to addressing circuitry.
Claim 3
Dependent Claim
24 words
The method of claim 1 , further comprising forming a third insulating layer on the third layer to form a plurality of storage capacitors.
Claim 4
Dependent Claim
32 words
The method of claim 1 , wherein forming the first insulating layer between the substrate and the column bars comprises oxidizing a portion of the substrate to form the first insulating layer.
Claim 5
Dependent Claim
31 words
The method of claim 3 , further comprising filling the second plurality of trenches with insulating material by oxidizing a portion of the substrate exposed in the second plurality of trenches.
Claim 6
Dependent Claim
26 words
The method of claim 1 , further comprising splitting each word line into two word lines, the two word lines being electrically isolated from each other.
Claim 7
Dependent Claim
26 words
The method of claim 1 , wherein the plurality of column trenches extend into the substrate at least 0.6 μm below the surface of the substrate.
Claim 8
Independent Claim
256 words
A method of forming an integrated circuit, the method comprising: forming a first layer of a first conductivity type on a substrate, the first layer having a thickness in the range of 0.2 μm to 0.5 μm, the first layer comprising a more heavily doped layer within it, the more heavily doped layer having a thickness in the range of 0.1 μm to 0.25 μm; forming a second layer of a second conductivity type on the first layer; forming a third layer of the first conductivity type on the second layer, the third layer having a thickness in the range of 0.2 μm to 0.5 μm; forming a plurality of substantially parallel column trenches extending through the third, the second, and the first layers sufficiently deep to reach the substrate, the plurality of column trenches defining a plurality of column bars, wherein the width of a trench on the surface of the substrate is no more than 1 μm; forming a plurality of substantially parallel row trenches defining a plurality of row bars, the row trenches being substantially orthogonal to the column trenches, the plurality of row trenches extending through the third, the second and partially through the first layers, terminating above the more heavily doped layer, such that the more heavily doped layer serves as a plurality of bit lines; forming word lines in the plurality of row trenches, each word line comprising a conductive layer and being disposed in a row trench; and coupling the bit lines and the word lines to addressing circuitry.
Claim 9
Independent Claim
256 words
A method of forming an integrated circuit, the method comprising: forming a first layer of a first conductivity type on a substrate, the first layer having a thickness in the range of 0.2 μm to 0.5 μm, the first layer comprising a more heavily doped layer within it, the more heavily doped layer having a thickness in the range of 0.1 μm to 0.25 μm; forming a second layer of a second conductivity type on the first layer; forming a third layer of the first conductivity type on the second layer, the third layer having a thickness in the range of 0.2 μm to 0.5 μm; forming a plurality of substantially parallel column trenches extending through the third, the second, and the first layers sufficiently deep to reach the substrate, the plurality of column trenches defining a plurality of column bars, wherein the width of a trench on the surface of the substrate is no more than 1 μm; forming a plurality of substantially parallel row trenches defining a plurality of row bars, the row trenches being substantially orthogonal to the column trenches, the plurality of row trenches extending through the third, the second and partially through the first layers, terminating above the more heavily doped layer, such that the more heavily doped layer serves as a plurality of bit lines; forming word lines in the plurality of row trenches, each word line comprising a conductive layer and being disposed in a row trench; and coupling the bit lines and the word lines to addressing circuitry.
Claim 10
Dependent Claim
64 words
The method of claim 7 , further comprising forming a first insulating layer of about 10 nm thick on the third layer and a second insulating layer of about 100 nm thick on the first insulating layer before forming the plurality of the column trenches, the first and second insulating layers being removed after forming the word lines in the plurality of row trenches.
Claim 11
Dependent Claim
25 words
The method of claim 7 , further comprising filling the plurality of column trenches with an insulating material after forming the plurality of column trenches.
Claim 12
Dependent Claim
24 words
The method of claim 7 , further comprising forming an insulating layer on a surface of the row trenches before forming the word lines.
Claim 13
Dependent Claim
26 words
The method of claim 7 , further comprising splitting each word line into two word lines, the two word lines being electrically isolated from each other.
Claim 14
Independent Claim
181 words
A method of fabricating an integrated circuit, the method comprising: providing a substrate; forming a plurality of bit lines on the substrate; forming a plurality of access transistors on each of the bit lines, each access transistor including a first source/drain region shared by at least a portion of the bit line, a body region and a second source/drain region formed vertically thereupon; forming a plurality of isolation trenches in the substrate and orthogonal to the bit lines, each trench located between access transistors on the orthogonal bit lines; forming in a first one of the trenches a first word line that controls conduction between first and second source/drain regions of access transistors that are adjacent to a first side of the first trench; forming in a second one of the trenches, adjacent to the first trench, a second word line that controls conduction between first and second source/drain regions of access transistors that are adjacent to a first side of the second trench; and coupling the bit lines, the first word line and the second word line to addressing circuitry.
Claim 15
Independent Claim
181 words
A method of fabricating an integrated circuit, the method comprising: providing a substrate; forming a plurality of bit lines on the substrate; forming a plurality of access transistors on each of the bit lines, each access transistor including a first source/drain region shared by at least a portion of the bit line, a body region and a second source/drain region formed vertically thereupon; forming a plurality of isolation trenches in the substrate and orthogonal to the bit lines, each trench located between access transistors on the orthogonal bit lines; forming in a first one of the trenches a first word line that controls conduction between first and second source/drain regions of access transistors that are adjacent to a first side of the first trench; forming in a second one of the trenches, adjacent to the first trench, a second word line that controls conduction between first and second source/drain regions of access transistors that are adjacent to a first side of the second trench; and coupling the bit lines, the first word line and the second word line to addressing circuitry.
Claim 16
Dependent Claim
34 words
The method of claim 12 , wherein the first word line also controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the first trench.
Claim 17
Dependent Claim
34 words
The method of claim 12 , wherein the second word line also controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the second trench.
Claim 18
Dependent Claim
40 words
The method of claim 12 , further comprising forming, in the first trench, another first word line, which controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the first trench.
Claim 19
Dependent Claim
40 words
The method of claim 12 , further comprising forming, in the second trench, another second word line, which controls conduction between first and second source/drain regions of access transistors that are adjacent to a second side of the second trench.
Claim 20
Independent Claim
209 words
A method of fabricating an integrated circuit, the method comprising: forming a first conductivity type first source/drain region layer on a substrate; forming a second conductivity type body region layer on the first source/drain layer; forming a first conductivity type second source/drain region layer on the body region layer; forming a plurality of substantially parallel column isolation trenches extending through the second source/drain region layer, the body region layer, and the first source/drain region layer, thereby forming column bars between the column isolation trenches; providing an isolation material in the column isolation trenches; forming a plurality of substantially parallel row isolation trenches, orthogonal to the column isolation trenches, extending through the second source/drain region layer, the body region layer, and at least partially into the first source/drain region layer in the column bars, such that the first source/drain region layer in the column bars serves as a bit line, the row isolation trenches also extending at least partially into the isolation material in the column isolation trenches, thereby forming row bars between the row isolation trenches; forming an insulating layer at the base of the row isolation trenches; forming conductive word lines in the row isolation trenches; and coupling the bit lines and the word lines to addressing circuitry.
Claim 21
Independent Claim
209 words
A method of fabricating an integrated circuit, the method comprising: forming a first conductivity type first source/drain region layer on a substrate; forming a second conductivity type body region layer on the first source/drain layer; forming a first conductivity type second source/drain region layer on the body region layer; forming a plurality of substantially parallel column isolation trenches extending through the second source/drain region layer, the body region layer, and the first source/drain region layer, thereby forming column bars between the column isolation trenches; providing an isolation material in the column isolation trenches; forming a plurality of substantially parallel row isolation trenches, orthogonal to the column isolation trenches, extending through the second source/drain region layer, the body region layer, and at least partially into the first source/drain region layer in the column bars, such that the first source/drain region layer in the column bars serves as a bit line, the row isolation trenches also extending at least partially into the isolation material in the column isolation trenches, thereby forming row bars between the row isolation trenches; forming an insulating layer at the base of the row isolation trenches; forming conductive word lines in the row isolation trenches; and coupling the bit lines and the word lines to addressing circuitry.
Claim 22
Dependent Claim
16 words
The method of claim 17 , further comprising forming an insulating layer underlying the column bars.
Claim 23
Dependent Claim
27 words
The method of claim 17 , further comprising etching portions of the word lines to provide separate word lines on each side of the row isolation trenches.
References Cited (Backward Citations)
US4965651A
Cited
US4020364A
Cited
US3931617A
Cited
US4716314A
Cited
US4051354A
Cited
US4313106A
Cited
US4617649A
Cited
US4617649B1
Cited
US4604162A
Cited
US5208657A
Cited
US4630088A
Cited
US4766569A
Cited
US4761768A
Cited
US4673962A
Cited
US5102817A
Cited
US4677589A
Cited
US4740826A
Cited
US4663831A
Cited
US4701423A
Cited
US4845537A
Cited
US5017504A
Cited
US4761385A
Cited
US5427972A
Cited
US4920515A
Cited
US4949138A
Cited
US5001526A
Cited
US4888735A
Cited
US5072269A
Cited
US4906590A
Cited
US5057896A
Cited
US4958318A
Cited
US4920065A
Cited
US5327380B1
Cited
US5327380A
Cited
US5021355A
Cited
US5028977A
Cited
US5316962A
Cited
US5083047A
Cited
US5006909A
Cited
US5010386A
Cited
US5410169A
Cited
US5216266A
Cited
US5107459A
Cited
US5276343A
Cited
US5177576A
Cited
US5378914A
Cited
US4987089A
Cited
US5087581A
Cited
US5140388A
Cited
US5223081A
Cited
US5110752A
Cited
US5341331A
Cited
US5202278A
Cited
US5376575A
Cited
US5504357A
Cited
US5221867A
Cited
US5177028A
Cited
US5191509A
Cited
US5329481A
Cited
US5156987A
Cited
US5926412A
Cited
US5308782A
Cited
US5528062A
Cited
US5466625A
Cited
US5416736A
Cited
US5320880A
Cited
US5414288A
Cited
US5385853A
Cited
US5266514A
Cited
US5422499A
Cited
US5391911A
Cited
US5438009A
Cited
US5616934A
Cited
US5519236A
Cited
US5396452A
Cited
US5644540A
Cited
US5392245A
Cited
US5445986A
Cited
US5460316A
Cited
US5483094A
Cited
US5443992A
Cited
US5393704A
Cited
US5396093A
Cited
US5492853A
Cited
US5574299A
Cited
US5414287A
Cited
US5460988A
Cited
US5422296A
Cited
US5495441A
Cited
US5627390A
Cited
US5432739A
Cited
US5563083A
Cited
US5440158A
Cited
US5483487A
Cited
US5834814A
Cited
US5705415A
Cited
US5593912A
Cited
US5508542A
Cited
US5581101A
Cited
US5646900A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-25 | 2005-08-27 | 2006-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-25 | 2009-08-27 | 2010-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-25 | 2013-08-27 | 2014-02-26 | $7700.00 | Window Closed / Lapsed |