Dynamic random access memory

Claim 2

A dynamic random access memory comprising: a plurality of memory cells at the intersections of word lines and bit lines, said memory cells being coupled to a folded bit line, each memory cell comprising: a storage capacitor for storing charge representative of a stored value; a first, write transistor coupled to a first plate of said storage capacitor and a first bit line; and a second, read transistor having a first terminal thereof coupled to a first terminal of a third transistor and a second terminal coupled to a second bit line, said third transistor comprising a gate coupled to said first plate of said storage capacitor, said word line coupled with a gate of both said read transistor and said write transistor; and a sense amplifier coupled to said folded bit line.

Claim 3

A dynamic random access memory as recited in claim 1 further comprising a fourth transistor coupled to said first bit line and ground, said fourth transistor permitting said first bit line to lose voltage at a reduced rate compared to said second bit line when reading a high charge from said storage capacitor

Claim 4

A dynamic random access memory for integrated circuits, comprising a plurality of memory cells, each memory cell comprising: a storage capacitor in a first semiconductor layer; transistor elements in a second semiconductor layer, above said first semiconductor layer, wherein said first and second semiconductor layers are substantially parallel with a surface of a substrate wafer, and said capacitor is directly beneath said transistor elements; and said storage capacitor is coupled to said transistor elements.

Claim 5

A dynamic random access memory for integrated circuits, comprising a plurality of memory cells, each memory cell comprising: a storage capacitor in a first semiconductor layer; transistor elements in a second semiconductor layer, above said first semiconductor layer, wherein said first and second semiconductor layers are substantially parallel with a surface of a substrate wafer, and said capacitor is directly beneath said transistor elements; and said storage capacitor is coupled to said transistor elements.

Claim 6

A dynamic random access memory as recited in claim 3 wherein said capacitor is a trench capacitor.

Claim 7

A dynamic random access memory as recited in claim 3 wherein said capacitor is a planar capacitor.

Claim 8

The dynamic random access memory of claim 2 wherein said second bit line being pulled low by said sense amplifier upon reading said high charge from said storage capacitor and said first bit line being pulled high by said sense amplifier upon reading said high charge from said storage capacitor.

Claim 9

The dynamic random access memory of claim 6 wherein said second bit line being at a low level and said first bit being at a high level when writing a high charge to said storage capacitor.

Claim 10

The dynamic random access memory of claim 1 further comprising a fourth transistor coupled to said second bit line and a high potential level, wherein said second bit line being pulled up to a high level when reading a low charge from said storage capacitor and said second bit line being pulled down to a low level when reading a high charge from said storage capacitor.

Claim 11

The dynamic random access memory of claim 1 further comprising a fourth transistor coupled to one of said bit lines of said folded bit line, said fourth transistor displacing the potential levels on said bit lines relative to each others in the opposite direction of the displacement caused by a reading of said stored charge at a rate less than the rate of displacement caused by said reading of said stored charge.

Claim 12

The dynamic random access memory of claim 1 further comprising a fourth transistor coupled to said second bit line and a high potential level, said second bit line being pulled lower than said first bit line against a source current from said fourth transistor when reading a high charge from said storage capacitor, said fourth transistor pulling said second bit line higher than said first bit line when reading a low charge from said storage capacitor.

Claim 13

A dynamic random access memory access comprising: a plurality of memory cells at the intersections of word lines and bit lines, said memory cells being coupled to a folded bit line, each memory cell comprising: a storage capacitor for storing charge representative of a stored value; a first, write transistor coupled to a first plate of said storage capacitor and a first bit line; and a second, read transistor having a first terminal thereof coupled to a first terminal of a third transistor and a second terminal coupled to a second bit line, said read transistor having a lower switching threshold than said write transistor, said third transistor comprising a gate coupled to said first plate of said storage capacitor, said word line coupled with a gate of both said read transistor and said write transistor; a fourth transistor coupled to said first bit line and ground, said fourth transistor permitting said first bit line to lose voltage at a reduced rate as compared to said second bit line when reading a high charge from said storage capacitor; a fifth transistor coupled to said first bit line and a clamp line having a clamp level, said clamp level being intermediate to ground and a switching threshold of said write transistor; and a sense amplifier coupled to said folded bit line.

Claim 14

A dynamic random access memory access comprising: a plurality of memory cells at the intersections of word lines and bit lines, said memory cells being coupled to a folded bit line, each memory cell comprising: a storage capacitor for storing charge representative of a stored value; a first, write transistor coupled to a first plate of said storage capacitor and a first bit line; and a second, read transistor having a first terminal thereof coupled to a first terminal of a third transistor and a second terminal coupled to a second bit line, said read transistor having a lower switching threshold than said write transistor, said third transistor comprising a gate coupled to said first plate of said storage capacitor, said word line coupled with a gate of both said read transistor and said write transistor; a fourth transistor coupled to said first bit line and ground, said fourth transistor permitting said first bit line to lose voltage at a reduced rate as compared to said second bit line when reading a high charge from said storage capacitor; a fifth transistor coupled to said first bit line and a clamp line having a clamp level, said clamp level being intermediate to ground and a switching threshold of said write transistor; and a sense amplifier coupled to said folded bit line.