EP0175378A2
Expired / Lapsed
EP
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Dynamic random access memory (DRAM)
Assignee: Fujitsu Ltd
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Filing: 1985-09-20
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Granted: —
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Expires: 2005-09-20
Abstract
Abstract 57 A three MIS transistor dynamic random access memory (DRAM) cell having a two-stored structure, affording a high packing density, comprises a write select transistor (T 2 ) disposed over a read select transistor (T i ). The transistors (T i , T 2 ) are separated from one another by an insulator layer (7), and a drain region of the write select transistor (T 2 ) is shared with the underlying read select transistor (T i ). A storage transistor (T 3 ) and the read select transistor (T i ) are formed on a silicon substrate in the same level. Channel regions (Ch1, Ch3) of the two transistors are connected to one another and each is used as a diffusion (source or drain) region of the other of the two transistors. A write select line (WL) and a read select line (RL) may be combined into a single control line: a write/read select line (WRL), saving one line to obtain higher packing density. In such a cell, gate electrodes of both read select and write select transistors (T 1 , T 2 ) are connected to the write/read line (WRL). These transistors are distinguished from each other by having different threshold voltage levels from one another.
Inventors
- 👤 Motoo C/O Fujitsu Limited Nakano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 12:10
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/20; H10D; H10D88/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; H10B12/01
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
232 words
A three-transistor cell for a dynamic random access memory, the cell comprising a read select transistor (T1), having a drain (3a) connected to a data bit line (DL) of the memory, and a gate (5,15) connected to a read select line (RL, WRL) of the memory, a stor ge transistor (T3), having a drain (Ch1) connected to a source (Ch3) of the read select transistor (T 1 ) and a source (3b) connected to a ground line (GND) of the memory, and a write select transistor (T 2 ), having a source (9b) connected to a gate (9b) of the storage transistor, a gate (10,15) connected to a write select line (WL, WRL) of the memory, and a drain (9a) connected to the data bit line (DL), characterised in that the write select transistor (T 2 ) is formed over the read select transistor (T 1 ), with an interposed insulator layer (6, 7; 6, 7, 10), the drain (9a) of the write select transistor being connected directly to the drain (3a) of the read select transistor through a window or opening in the interposed insulator layer, and in that the source region (9b) of the write select transistor (T 2 ) acts also as the gate of the storage transistor (T 3 ) which is otherwise provided on the same side of the interposed insulator layer as the read select transistor.
Claim 2
Dependent Claim
232 words
A three-transistor cell for a dynamic random access memory, the cell comprising a read select transistor (T1), having a drain (3a) connected to a data bit line (DL) of the memory, and a gate (5,15) connected to a read select line (RL, WRL) of the memory, a stor ge transistor (T3), having a drain (Ch1) connected to a source (Ch3) of the read select transistor (T 1 ) and a source (3b) connected to a ground line (GND) of the memory, and a write select transistor (T 2 ), having a source (9b) connected to a gate (9b) of the storage transistor, a gate (10,15) connected to a write select line (WL, WRL) of the memory, and a drain (9a) connected to the data bit line (DL), characterised in that the write select transistor (T 2 ) is formed over the read select transistor (T 1 ), with an interposed insulator layer (6, 7; 6, 7, 10), the drain (9a) of the write select transistor being connected directly to the drain (3a) of the read select transistor through a window or opening in the interposed insulator layer, and in that the source region (9b) of the write select transistor (T 2 ) acts also as the gate of the storage transistor (T 3 ) which is otherwise provided on the same side of the interposed insulator layer as the read select transistor.
Claim 3
Dependent Claim
57 words
A cell as claimed in claim 1, wherein a channel region (Ch1) of the read select transistor is directly connected to a channel region (Ch3) of the storage transistor, the former channel region (Ch1) also acting as drain of the storage transistor and the latter channel region (Ch3) also acting as source of the read select transistor.
Claim 4
Dependent Claim
25 words
A cell as claimed in claim 1 or 2, wherein the read select transistor and the storage transistor are constituted as a dual gate transistor.
Claim 5
Dependent Claim
65 words
A cell as claimed in claim 1, 2 or 3, wherein the read select transistor (T 1 ) and the write select transistor (T 2 ) share a common gate (15) connected to a combined read/write select line (WRL) of the memory, the read select transistor and the write select transistor having respective gate insulator layers (4, 10) and respective different threshold voltages (Vth1, Vth2).
Claim 6
Dependent Claim
223 words
A three-transistor cell for a dynamic random access memory (DRAM) formed on a silicon substrate (1), the cell comprising a read select MIS transistor (T 1 ), for selecting said cell for a reading operation, having a first drain region (3a) and a first channel region (Ch1) formed in said silicon substrate (1), a write select MIS transistor (T 2 ), for selecting said cell for a write operation, formed in a semiconductor layer (8) formed on an insulator layer (7) over said read select MIS transistor (T 1 ), having a source region (9b), a second drain region (9a) connected directly to said first drain region (3a) of said read select transistor (T 1 ) through a contact window (13a) opened in said insulator layer (7), and a storage MIS transistor (T3), for storing an information signal, formed on said silicon substrate (1), having a second channel region (Ch3) which is directly connected to said first channel region (Ch1) of said read select transistor (T 1 ), and utilizing said source region (9b) of said write select transistor (T 2 ) as its gate electrode, said first channel region (Ch1) of said read select transistor (T 1 ) and said second channel region (Ch3) of said storage transistor (T 3 ), being formed in the same level in said silicon substrate (1),
Claim 7
Dependent Claim
223 words
A three-transistor cell for a dynamic random access memory (DRAM) formed on a silicon substrate (1), the cell comprising a read select MIS transistor (T 1 ), for selecting said cell for a reading operation, having a first drain region (3a) and a first channel region (Ch1) formed in said silicon substrate (1), a write select MIS transistor (T 2 ), for selecting said cell for a write operation, formed in a semiconductor layer (8) formed on an insulator layer (7) over said read select MIS transistor (T 1 ), having a source region (9b), a second drain region (9a) connected directly to said first drain region (3a) of said read select transistor (T 1 ) through a contact window (13a) opened in said insulator layer (7), and a storage MIS transistor (T3), for storing an information signal, formed on said silicon substrate (1), having a second channel region (Ch3) which is directly connected to said first channel region (Ch1) of said read select transistor (T 1 ), and utilizing said source region (9b) of said write select transistor (T 2 ) as its gate electrode, said first channel region (Ch1) of said read select transistor (T 1 ) and said second channel region (Ch3) of said storage transistor (T 3 ), being formed in the same level in said silicon substrate (1),
Claim 8
Dependent Claim
116 words
A three-transistor cell of a dynamic random access memory (DRAM) of claim 5, wherein said read select transistor T 1 ) and said write select transistor (T 2 ) formed over aid read select transistor (T 1 ) share a common gate electrode (15-Fig. 3 (c)) with each other, said common gate electrode (15) being disposed between said read select transistor (T 1 ) and said write select transistor (T 2 ) and effective for the respective transistors through respective gate insulator layers (4, 10), said read select transistor (T 1 ) and said write select transistor (T 2 ) having different respective threshold voltages (Vth1, Vth2) so that the two transistors can be selectively driven.
Claim 9
Dependent Claim
34 words
A three-transistor cell of a dynamic random access memory (DRAM) of claim 5, wherein said storage transistor (T 3 ) further has a gate electrode, side walls of which are covered by insulator layers.
Claim 10
Dependent Claim
28 words
A three-transistor cell of a dynamic random access memory (DRAM) of claim 5, wherein the side walls of said common gate electrode (15) are covered by insulator layers.
Claim 11
Dependent Claim
216 words
A transistor cell of a dynamic random access memory (DRAM) comprising a data bit line (DL) for outputting and inputting an information signal, a shared write/read select line (WRL) for selecting said cell for writing an information signal therein or for reading out an information signal stored therein, a ground line-(GND), a read select MIS transistor (T 1 ), a write select MIS transistor (T 2 ), and a storage MIS transistor (T 3 ), each MIS transistor having a drain, a source and a gate; wherein: the drain (9a), the source (9b) and the gate (15) of said write transistor (T 2 ) are respectively connected to said data bit line (DL), to the gate (9b) of said storage transistor (T 3 ), and to said write/read select line (WRL); the drain (3a), the source (Ch3) and the gate (15) of said read transistor (T 1 ) are respectively connected to said data bit line (DL), to the drain (Ch1) of said storage MIS transistor (T 3 ) and to the write/read select line (WRL); the source (3b) of said storage transistor is connected to said ground line (GND), and said read MIS transistor (T 1 ) and said write MIS transistor (T 2 ) have threshold voltage levels (Vth1, Vth2) differing from each other.
Claim 12
Dependent Claim
216 words
A transistor cell of a dynamic random access memory (DRAM) comprising a data bit line (DL) for outputting and inputting an information signal, a shared write/read select line (WRL) for selecting said cell for writing an information signal therein or for reading out an information signal stored therein, a ground line-(GND), a read select MIS transistor (T 1 ), a write select MIS transistor (T 2 ), and a storage MIS transistor (T 3 ), each MIS transistor having a drain, a source and a gate; wherein: the drain (9a), the source (9b) and the gate (15) of said write transistor (T 2 ) are respectively connected to said data bit line (DL), to the gate (9b) of said storage transistor (T 3 ), and to said write/read select line (WRL); the drain (3a), the source (Ch3) and the gate (15) of said read transistor (T 1 ) are respectively connected to said data bit line (DL), to the drain (Ch1) of said storage MIS transistor (T 3 ) and to the write/read select line (WRL); the source (3b) of said storage transistor is connected to said ground line (GND), and said read MIS transistor (T 1 ) and said write MIS transistor (T 2 ) have threshold voltage levels (Vth1, Vth2) differing from each other.
Claim 13
Dependent Claim
43 words
A three-transistor cell of a dynamic random access memory (DRAM) of claim 5, wherein said semiconductor layer (8) in which said write select transistor (T 2 ) is formed in a single crystal silicon layer fabricated utilizing a silicon on insulator (SOI) technology.
Claim 14
Dependent Claim
41 words
A three-transistor cell of a dynamic random access memory (DRAM) of claim 5 or 6, wherein said read select MIS transistor (T 1 ) and said storage MIS transistor (T 3 ) are replaced by a dual gate electrode MIS transistor.
References Cited (Backward Citations)
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