US6180442B1 — Bipolar transistor with an inhomogeneous emitter …

Claim 1

Independent Claim 274 words

A method for fabricating an integrated circuit including a bipolar transistor of NPN type, including the following steps: forming an N-type epitaxial layer on a P-type substrate, a buried layer being provided at least at a location of a bipolar transistor; forming a thick oxide layer having an opening at a base-emitter region of the bipolar transistor; forming a first P-type doped polysilicon or amorphous silicon layer and a second oxide layer; forming an opening in the doped polysilicon layer or the silicon layer and the oxide layer at a center of the base-emitter region of the bipolar transistor; diffusing dopants contained in the first silicon layer in the epitaxial layer, to form an extrinsic base of the bipolar transistor, wherein during said diffusion a thin oxide layer forms on exposed silicon surfaces; depositing a layer of silicon nitride and a second layer of polysilicon over the opening, and anisotropically etching the second layer of polysilicon to form spacers at vertical sides of the opening; removing exposed parts of said silicon nitride and overetching said silicone nitrade under the spacers; removing the thin oxide layer at locations where the silicon nitride has been overetched; forming an N-type collector region by implantation; implanting a P-type dopant to form an intrinsic base region of the bipolar transistor; depositing a third highly-doped N-type polysilicon layer into the opening and anisotropically etching to leave a part of the third polysilicon layer where the silicon nitride has been overetched; and depositing a fourth N-type doped polysilicon layer over the opening and diffusing dopants contained in the third and fourth layers to form an emitter region of the bipolar transistor.

Claim 2

Independent Claim 274 words

A method for fabricating an integrated circuit including a bipolar transistor of NPN type, including the following steps: forming an N-type epitaxial layer on a P-type substrate, a buried layer being provided at least at a location of a bipolar transistor; forming a thick oxide layer having an opening at a base-emitter region of the bipolar transistor; forming a first P-type doped polysilicon or amorphous silicon layer and a second oxide layer; forming an opening in the doped polysilicon layer or the silicon layer and the oxide layer at a center of the base-emitter region of the bipolar transistor; diffusing dopants contained in the first silicon layer in the epitaxial layer, to form an extrinsic base of the bipolar transistor, wherein during said diffusion a thin oxide layer forms on exposed silicon surfaces; depositing a layer of silicon nitride and a second layer of polysilicon over the opening, and anisotropically etching the second layer of polysilicon to form spacers at vertical sides of the opening; removing exposed parts of said silicon nitride and overetching said silicone nitrade under the spacers; removing the thin oxide layer at locations where the silicon nitride has been overetched; forming an N-type collector region by implantation; implanting a P-type dopant to form an intrinsic base region of the bipolar transistor; depositing a third highly-doped N-type polysilicon layer into the opening and anisotropically etching to leave a part of the third polysilicon layer where the silicon nitride has been overetched; and depositing a fourth N-type doped polysilicon layer over the opening and diffusing dopants contained in the third and fourth layers to form an emitter region of the bipolar transistor.

Claim 3

Dependent Claim 20 words

A method according to claim 1 , wherein the first silicon nitride layer has a thickness of around 50 nm.

Claim 4

Dependent Claim 33 words

A method according to claim 1 , wherein the spacers have a base length of around 200 nm and the overetching removes the silicon nitride layer across a width of around 100 nm.

Claim 5

Dependent Claim 34 words

A method according to claim 1 , wherein the third polysilicon layer is doped to about 10 20 at./cm 3 and is from 10 to 100 times more doped than the fourth polysilicon layer.

Claim 6

Dependent Claim 33 words

A method according to claim 1 , including the step of depositing a second silicon nitride layer between the first P-type doped polysilicon or amorphous silicon layer and the second encapsulation oxide layer.

Claim 7

Dependent Claim 21 words

A method according to claim 1 Wherein the epitaxial layer has a thickness in a range of 1 to 1.2 μm.

Claim 8

Dependent Claim 14 words

A method according to claim 1 wherein said buried layer is of the N-type.

Claim 9

Dependent Claim 21 words

A method according to claim 1 wherein the integrated circuit includes a MOS transistor and said method including said MOS transistors.

Claim 10

Dependent Claim 20 words

A method according to claim 1 wherein the thick oxide layer is formed with at least one thin oxide region.

Claim 11

Dependent Claim 22 words

A method according to claim 9 including implanting N-type wells and P-type wells in the epitaxial layer under respective thin oxide regions.

Claim 12

Dependent Claim 17 words

A method according to claim 10 including forming a collector well of N-type in the epitaxial layer.

Claim 13

Dependent Claim 14 words

A method according to claim 11 including forming insulated gates of the MOS transistors.

Claim 14

Dependent Claim 31 words

A method according to claim 12 including inking source and drain implants of the N-channels transistors in the P wells, and performing a highly-doped N-type diffusion at the surface or well.

Claim 15

Dependent Claim 28 words

A method according to claim 1 including providing a protection layer including a silicon oxide layer followed by a silicon nitride layer, both deposited over the entire structure.

Claim 16

Dependent Claim 35 words

A method according to claim 14 wherein the silicon oxide layer is deposited to a thickness of about 20 nm and said silicon nitride layer is deposited to a thickness o f about 30 nm.

Claim 17

Dependent Claim 36 words

A method according to claim 1 including implanting a P-type doping in the first polysilicon layer by implanting boron at a very high dose low energy BF 2 (10 15 to 10 16 at./cm 2 ).

Claim 18

Dependent Claim 33 words

A method according to claim 1 wherein the N-type collector doping is performed at medium dose and high energy on the order of 10 12 to 10 14 at./cm 2 under 500 keV.

Claim 19

Independent Claim 30 words

A method according to clam 1 wherein the implanting for form the intrinsic base is with low energy boron on the order of 10 13 at./cm 2 under 5 keV.

Claim 20

Independent Claim 30 words

A method according to clam 1 wherein the implanting for form the intrinsic base is with low energy boron on the order of 10 13 at./cm 2 under 5 keV.

Claim 21

Independent Claim 185 words

A method of fabricating an integrated circuit including a bipolar transistor, said method comprising the steps of: forming an epitaxial layer on a substrate; forming a thick oxide layer with at least one thin oxide region over the epitaxial layer; forming a first layer of one of a doped polysilicon and an amorphous silicon; opening said first layer at a base-emitter region of the bipolar transistor; diffusing a dopant contained in the first silicon layer into the underlying epitaxial layer to form an extrinsic base of the bipolar transistor; depositing a first layer of silicon nitride and a second layer of polysilicon over the base-emitter region, and etching the second polysilicon layer to provide vertically disposed spacers at the base-emitter region; removing exposed silicon nitride and overetching it under the spacers; implanting a collector doping; forming an intrinsic base of the bipolar transistor; depositing into the base-emitter region a third polysilicon layer so that it penetrates into an overetched area under the spacers; and depositing into the base-emitter region a fourth polysilicon layer to form at least part of an emitter of the bipolar transistor.

Claim 22

Independent Claim 185 words

A method of fabricating an integrated circuit including a bipolar transistor, said method comprising the steps of: forming an epitaxial layer on a substrate; forming a thick oxide layer with at least one thin oxide region over the epitaxial layer; forming a first layer of one of a doped polysilicon and an amorphous silicon; opening said first layer at a base-emitter region of the bipolar transistor; diffusing a dopant contained in the first silicon layer into the underlying epitaxial layer to form an extrinsic base of the bipolar transistor; depositing a first layer of silicon nitride and a second layer of polysilicon over the base-emitter region, and etching the second polysilicon layer to provide vertically disposed spacers at the base-emitter region; removing exposed silicon nitride and overetching it under the spacers; implanting a collector doping; forming an intrinsic base of the bipolar transistor; depositing into the base-emitter region a third polysilicon layer so that it penetrates into an overetched area under the spacers; and depositing into the base-emitter region a fourth polysilicon layer to form at least part of an emitter of the bipolar transistor.

Claim 23

Dependent Claim 24 words

A method according to claim 19 wherein the step of forming an epitaxial layer includes forming an N-type epitaxial layer on a P-type substrate.

Claim 24

Dependent Claim 24 words

A method according to claim 20 wherein the step of forming the thick oxide layer includes several said thin oxide regions for MOS transistors.

Claim 25

Dependent Claim 24 words

A method according to claim 21 wherein the epitaxial layer has a thickness in a range on the order of 1.0 to 1.2 μm.

Claim 26

Dependent Claim 20 words

A method according to claim 21 wherein the step of forming a first layer includes forming a P-type doped polysilicon.

Claim 27

Dependent Claim 13 words

A method according to claim 23 including forming a second encapsulation oxide layer.

Claim 28

Dependent Claim 30 words

A method according to claim 24 wherein both said first layer and said second encapsulation oxide layer are opened at the center of the base-emitter region of the bipolar transistor.

Claim 29

Dependent Claim 21 words

A method according to claim 25 including, during the diffusing step, forming a thin oxide layer on the apparent silicon surfaces.

Claim 30

Dependent Claim 18 words

A method according to claim 19 wherein the etching of the second polysilicon layer is by anisotropic etching.

Claim 31

Dependent Claim 20 words

A method according to claim 27 wherein the step of implanting a collector doping includes implanting an N-type collector doping.

Claim 32

Dependent Claim 19 words

A method according to claim 28 wherein the step of forming the intrinsic base includes implanting a P-type doping.

Claim 33

Dependent Claim 23 words

A method according to claim 29 wherein the step of depositing a third polysilicon layer includes depositing a third highly-doped N-type polysilicon layer.

Claim 34

Dependent Claim 25 words

A method according to claim 30 wherein the third highly-doped N-type polysilicon layer is etched anistropically to leave it in place in the overetched area.

Claim 35

Dependent Claim 38 words

A method according to claim 31 wherein the step of depositing a fourth polysilicon layer includes depositing a fourth N-type doped polysilicon layer and diffusing the doping contained in the third and fourth layers to form the emitter.

Claim 36

Dependent Claim 27 words

A method according to claim 19 wherein the step of depositing the first layer of silicon nitride includes depositing the layer to a thickness around 50 nm.

Claim 37

Dependent Claim 41 words

A method according to claim 19 wherein the step of providing the spacers includes providing the spacers with a base length around 200 nm, and the overetching of the silicon nitride layer is performed across a width of around 100 nm.

Claim 38

Dependent Claim 33 words

A method according to claim 19 wherein the third polysilicon layer is doped to about 10 20 at./cm 3 and is from 10 to 100 times as doped as the fourth polysilicon layer.

Claim 39

Dependent Claim 13 words

A method according to claim 19 including forming a second encapsulation oxide layer.

Claim 40

Dependent Claim 31 words

A method according to claim 36 including the step of depositing a second silicon nitride layer between the first polysilicon layer or amorphous silicon layer and the second encapsulation oxide layer.

Claim 41

Dependent Claim 35 words

A method according to claim 19 including, after the step of removing the apparent silicon nitride, the step of removing the thin oxide layer at the locations where the apparent silicon nitride has been overetched.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2004-01-30	2004-07-31	2005-01-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2008-01-30	2008-07-31	2009-01-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2012-01-30	2012-07-31	2013-01-30	$7700.00	Window Closed / Lapsed

Bipolar transistor with an inhomogeneous emitter in a BICMOS integrated circuit method

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