US5773349A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making ultrahigh speed bipolar transistor
Assignee: Samsung Electronics Co Ltd
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Filing: 1996-06-17
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Granted: 1998-06-30
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Expires: 2016-06-17
Abstract
Abstract An ultrahigh speed bipolar transistor has a base region which is formed from a P + base polysilicon sidewall using a self-alignment method, and a base junction window which is formed in order to minimize the collector-base junction capacity. In the method for fabricating this transistor, an insulation layer of oxide silicon or nitrogen silicon is formed under the base polysilicon layer. Accordingly, impurities from the base polysilicon layer do not diffuse into the epitaxial layer during the diffusion process. Instead, the extrinsic base region is formed by the diffusion of impurities from the polysilicon sidewall which is connected to the base polysilicon layer. Therefore the length of the entire base region is shortened. Furthermore, the junction area between the collector region is also lowered. Thus, the collector-base junction capacity is decreased and a higher operating speed is obtained.
Inventors
- 👤 Seog-Heon Ham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:01
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D10/421; H10D62/00; H10D62/10; H10D62/17; H10D62/177
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
263 words
A method of producing a bipolar transistor comprising: forming a triple layer on an epitaxial layer by successively forming a first insulation layer, a base polysilicon layer of a first conductivity type and a second insulating layer, said epitaxial layer being of a second conductivity type and having an active region and a collector region; opening an aperture through said triple layer to expose a portion of said active region of said epitaxial layer; forming polysilicon sidewalls of said first conductivity type on exposed portions of said triple layer inside said aperture, said polysilicon sidewalls being connected to portions of said base polysilicon layer exposed in said aperture and portions of said exposed portion of said active region adjacent to said triple layer; introducing impurities of said first conductivity type into remaining portions of said exposed portion of said active region of said epitaxial layer between said polysilicon sidewalls; forming insulating sidewalls over said polysilicon sidewalls and said portions of said base polysilicon layer exposed in said aperture; forming an emitter polysilicon layer of said second conductivity type connected to said remaining portions of said exposed portion of said active region of said epitaxial layer; forming a collector polysilicon layer of said second conductivity type on said collector region of said epitaxial layer, said collector polysilicon layer being insulated from said emitter polysilicon layer; and forming an emitter region and a base region in said active region of said epitaxial layer by simultaneously diffusing said implanted impurities, impurities of said emitter polysilicon layer, and impurities of said polysilicon sidewalls into said epitaxial layer.
Claim 2
Independent Claim
263 words
A method of producing a bipolar transistor comprising: forming a triple layer on an epitaxial layer by successively forming a first insulation layer, a base polysilicon layer of a first conductivity type and a second insulating layer, said epitaxial layer being of a second conductivity type and having an active region and a collector region; opening an aperture through said triple layer to expose a portion of said active region of said epitaxial layer; forming polysilicon sidewalls of said first conductivity type on exposed portions of said triple layer inside said aperture, said polysilicon sidewalls being connected to portions of said base polysilicon layer exposed in said aperture and portions of said exposed portion of said active region adjacent to said triple layer; introducing impurities of said first conductivity type into remaining portions of said exposed portion of said active region of said epitaxial layer between said polysilicon sidewalls; forming insulating sidewalls over said polysilicon sidewalls and said portions of said base polysilicon layer exposed in said aperture; forming an emitter polysilicon layer of said second conductivity type connected to said remaining portions of said exposed portion of said active region of said epitaxial layer; forming a collector polysilicon layer of said second conductivity type on said collector region of said epitaxial layer, said collector polysilicon layer being insulated from said emitter polysilicon layer; and forming an emitter region and a base region in said active region of said epitaxial layer by simultaneously diffusing said implanted impurities, impurities of said emitter polysilicon layer, and impurities of said polysilicon sidewalls into said epitaxial layer.
Claim 3
Dependent Claim
35 words
A method of claim 1 wherein said step of forming said polysilicon sidewalls includes adjusting a height so that tops of said polysilicon sidewalls are adjacent to an upper surface of said base polysilicon layer.
Claim 4
Dependent Claim
35 words
A method of claim 1 wherein said step of forming said insulating sidewalls includes adjusting a height so that tops of said insulating sidewalls are adjacent to an upper surface of said second insulating layer.
Claim 5
Dependent Claim
35 words
A method of claim 2 wherein said step of forming said insulating sidewalls includes adjusting a height so that tops of said insulating sidewalls are adjacent to an upper surface of said second insulating layer.
Claim 6
Dependent Claim
21 words
A method of claim 1 wherein said first conductivity type is N type and said second conductivity type is P type.
Claim 7
Dependent Claim
114 words
A method of claim 1 wherein said step of forming said polysilicon sidewalls includes: depositing polysilicon of said first conductivity type in said aperture; etching said polysilicon by reactive ion etching to expose said remaining portions of said exposed portion of said active region of said epitaxial layer, and to form said polysilicon sidewalls on sides of said aperture; coating said aperture with a photoresist film and etching by reactive ion etching to expose tops of said polysilicon sidewalls; overetching said polysilicon sidewalls to adjust a height so that said tops of said polysilicon sidewalls are adjacent to an upper surface of said base polisilicon layer; and removing remaining portions of said photoresist film.
Claim 8
Dependent Claim
37 words
A method of claim 6, further comprising: oxidizing said polysilicon sidewalls and said remaining portions of said exposed portion of said active region of said epitaxial layer before said step of implanting impurities into said remaining portions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |