US5403757A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of producing a double-polysilicon bipolar transistor
Assignee: NEC Corp
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Filing: 1993-08-30
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Granted: 1995-04-04
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Expires: 2013-08-30
Abstract
Abstract A double-layered structure of the base electrode corresponding to the emitter diffused-region 15 to be formed, which consists of the first and second conducting films 5, 6. This structure effects to prevent the surface of the silicon substrate in the emitter diffused-region to be formed from being etched away by the overetching for forming the base electrode, with much reduction of leakage current due to the consequent damage to the silicon-substrate surface in the emitter diffused-region to be formed, leading to improvement in transistor yield.
Inventors
- 👤 Hisamitsu Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:24
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
242 words
A method of fabricating a bipolar transistor comprising the steps of selectively forming an insulating film to expose a surface of a part of a collector region, said surface of said part of said collector region comprising a first portion and a second portion surrounding said first portion, forming a first polysilicon layer on said surface of said part of said collector region with an area larger than said first portion, forming a second polysilicon layer on said first polysilicon layer, said second polysilicon layer being elongated over said insulating film to be in direct contact with said insulating film, said second polysilicon layer having a first part formed on said first polysilicon layer and a second part formed directly on said insulating film, performing a selective removal of respective portions of said first and second parts of said second polysilicon layer and stopping said selective removal at a time when said insulating film is exposed, said first polysilicon layer remaining to cover said surface of said part of said collector region, followed by forming a hole in said first polysilicon layer to expose said first portion of said surface of said part of said collector region, introducing impurities from said first and second polysilicon layers into said collector region to form an extrinsic base region, and introducing impurities into said first portion of said surface of said part of said collector region through said hole to form an intrinsic base region.
Claim 2
Independent Claim
242 words
A method of fabricating a bipolar transistor comprising the steps of selectively forming an insulating film to expose a surface of a part of a collector region, said surface of said part of said collector region comprising a first portion and a second portion surrounding said first portion, forming a first polysilicon layer on said surface of said part of said collector region with an area larger than said first portion, forming a second polysilicon layer on said first polysilicon layer, said second polysilicon layer being elongated over said insulating film to be in direct contact with said insulating film, said second polysilicon layer having a first part formed on said first polysilicon layer and a second part formed directly on said insulating film, performing a selective removal of respective portions of said first and second parts of said second polysilicon layer and stopping said selective removal at a time when said insulating film is exposed, said first polysilicon layer remaining to cover said surface of said part of said collector region, followed by forming a hole in said first polysilicon layer to expose said first portion of said surface of said part of said collector region, introducing impurities from said first and second polysilicon layers into said collector region to form an extrinsic base region, and introducing impurities into said first portion of said surface of said part of said collector region through said hole to form an intrinsic base region.
Claim 3
Dependent Claim
50 words
The method as claimed in claim 1, wherein said area of said first polysilicon layer is smaller than said surface of said part of said collector region to form an exposed portion in said second portion, said second polysilicon being formed to cover said exposed portion of said second portion.
Claim 4
Dependent Claim
35 words
The method as claimed in claim 1, wherein said area of said first polysilicon layer is larger than said surface of said part of said collector region to thereby being elongated over said insulating film.
Claim 5
Dependent Claim
55 words
The method as claimed in claim 1, wherein said selective removal is performed by a plasma etching method in which said second polysilicon layer is exposed to a plasma and said selective removal is stopped when a change of plasma spectrum occurs in said plasma due to said insulating film being exposed to said plasma.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |