Process for simultaneously fabricating a bipolar transistor and a field-effect transistor

Claim 1

A process for the simultaneous fabrication of a bipolar transistor and a field-effect transistor at a face of a semiconductor layer having a first conductivity type, comprising the steps of: simultaneously forming first and second tank regions to be of a second conductivity type opposite said first conductivity type into said face of the semiconductor layer and to be spaced apart; forming a third tank region of said first conductivity type at the face within said first tank region; forming a conductive gate insulatively disposed over said second tank region; simultaneously implanting (a) source/drain regions of the second conductivity type for the field effect transistor into the face of the second tank region and at least partially aligned to said conductive gate, (b) an emitter of the second conductivity type into the face of the third tank region, and (c) a collector contact region of the second conductivity type into the face of the first tank region to be spaced from the third tank region; and forming a base region of a first conductivity type in said third tank region and apart from said emitter; wherein said first tank region is formed by selectively implanting dopant of said second conductivity type into the semiconductor layer at the location in which the first tank region is to be formed and the second tank region is formed by selectively implanting said dopant of said second conductivity type into the semiconductor layer at the location in which the second tank region is to be formed.