US4918026A
Expired / Lapsed
US
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Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip
Assignee: Delphi Technologies Inc
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Filing: 1989-03-17
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Granted: 1990-04-17
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Expires: 2009-03-17
Abstract
Abstract A process is used to form in a common substrate a PMOS transistor of the lightly doped drain (LDD) type, an NMOS transistor of the LDD type and a vertical n-p-n bipolar transistor. In particular: the steps used to form an n-type well for the PMOS transistor, and an n-type drain extension well for the NMOS transistor, are also used to form the n-type collector of the bipolar transistor; the steps used to form the p-type extension well for the PMOS transistor are also used to form the p-type base of the bipolar transistor, the source/drain implantation step for the NMOS transistor is also used to form the emitter and a contact region for the collector of the bipolar transistor; and the source/drain implantation step for the PMOS transistor is used to form a contact region for the base of the bipolar transistor.
Inventors
- 👤 Walter K. Kosiak
- 👤 Douglas R. Schnabel
- 👤 Jonathan D. Mann
- 👤 Jack D. Parrish
- 👤 Paul R. Rowlands, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:11
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D10/00; H10D10/01; H10D10/051; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
277 words
A process for forming in a common substrate a PMOS transistor of the lightly doped drain type, an NMOS transistor of the lightly doped drain type, and a vertical n-p-n bipolar transistor comprising the steps of: forming simultaneously in a p-type semiconductive substrate a first set of at least three relatively lightly doped n-type wells; forming simultaneously in a first and a second well of said first set of n-type wells a first and a second relatively lightly doped p-type well for serving as a lightly doped drain extension of the PMOS transistor and as the base of n-p-n transistor, respectively; forming simultaneously a relatively heavily doped n-type surface region in a third well of said first set of n-type wells for serving as the drain of an NMOS transistor and a relatively heavily doped n-type surface region in the p-type substrate for serving as the source of said NMOS transistor, a relatively heavily doped n-type surface region in the second p-type well for serving as the emitter of the n-p-n bipolar transistor and a relatively heavily doped n-type surface region in the second n-type well for serving as the collector contact region of the n-p-n bipolar transistor; forming simultaneously a relatively heavily doped p-type region in the first p-type well for serving as the drain of the PMOS transistor, a relatively heavily doped p-type surface region in the first n-type well for serving as the source of the PMOS transistor, and a relatively heavily doped p-type surface region in the second p-type well for serving as the base contact region of the n-p-n bipolar transistor; and providing polysilicon gate electrodes to the PMOS and NMOS transistors.
Claim 2
Dependent Claim
277 words
A process for forming in a common substrate a PMOS transistor of the lightly doped drain type, an NMOS transistor of the lightly doped drain type, and a vertical n-p-n bipolar transistor comprising the steps of: forming simultaneously in a p-type semiconductive substrate a first set of at least three relatively lightly doped n-type wells; forming simultaneously in a first and a second well of said first set of n-type wells a first and a second relatively lightly doped p-type well for serving as a lightly doped drain extension of the PMOS transistor and as the base of n-p-n transistor, respectively; forming simultaneously a relatively heavily doped n-type surface region in a third well of said first set of n-type wells for serving as the drain of an NMOS transistor and a relatively heavily doped n-type surface region in the p-type substrate for serving as the source of said NMOS transistor, a relatively heavily doped n-type surface region in the second p-type well for serving as the emitter of the n-p-n bipolar transistor and a relatively heavily doped n-type surface region in the second n-type well for serving as the collector contact region of the n-p-n bipolar transistor; forming simultaneously a relatively heavily doped p-type region in the first p-type well for serving as the drain of the PMOS transistor, a relatively heavily doped p-type surface region in the first n-type well for serving as the source of the PMOS transistor, and a relatively heavily doped p-type surface region in the second p-type well for serving as the base contact region of the n-p-n bipolar transistor; and providing polysilicon gate electrodes to the PMOS and NMOS transistors.
Claim 3
Dependent Claim
13 words
The process of claim 1 in which the semiconductive substrate is monocrystalline silicon.
Claim 4
Dependent Claim
300 words
A process for forming in a common substrate a PMOS transistor of the lightly doped drain type, an NMOS transistor of the lightly doped drain type, and a vertical n-p-n bipolar transistor comprising the steps of: forming simultaneously in a p-type semiconductive substrate a first set of at least three relatively lightly doped n-type wells; forming simultaneously in a first and a second well of said first set of n-type wells a first and a second relatively lightly doped p-type well for serving as a lightly doped drain extension of the PMOS transistor and as the base of n-p-n transistor, respectively; forming field oxide regions on the substrate, while driving in acceptor implanted ions for forming the first and second lightly doped p-type wells; forming simultaneously a relatively heavily doped n-type surface region in a third well of said first set of n-type wells for serving as the drain of an NMOS transistor and a relatively heavily doped n-type surface region in the p-type substrate for serving as the source of said NMOS transistor, a relatively heavily doped n-type surface region in the second p-type well for serving as the emitter of the n-p-n bipolar transistor and a relatively heavily doped n-type surface region in the second n-type well for serving as the collector contact region of the n-p-n bipolar transistor; forming simultaneously a relatively heavily doped p-type region in the first p-type well for serving as the drain of the PMOS transistor, a relatively heavily doped p-type surface region in the first n-type well for serving as the source of the PMOS transistor, and a relatively heavily doped p-type surface region in the second p-type well for serving as the base contact region of the n-p-n bipolar transistor; and providing polysilicon gate electrodes to the PMOS and NMOS transistors.
Claim 5
Dependent Claim
300 words
A process for forming in a common substrate a PMOS transistor of the lightly doped drain type, an NMOS transistor of the lightly doped drain type, and a vertical n-p-n bipolar transistor comprising the steps of: forming simultaneously in a p-type semiconductive substrate a first set of at least three relatively lightly doped n-type wells; forming simultaneously in a first and a second well of said first set of n-type wells a first and a second relatively lightly doped p-type well for serving as a lightly doped drain extension of the PMOS transistor and as the base of n-p-n transistor, respectively; forming field oxide regions on the substrate, while driving in acceptor implanted ions for forming the first and second lightly doped p-type wells; forming simultaneously a relatively heavily doped n-type surface region in a third well of said first set of n-type wells for serving as the drain of an NMOS transistor and a relatively heavily doped n-type surface region in the p-type substrate for serving as the source of said NMOS transistor, a relatively heavily doped n-type surface region in the second p-type well for serving as the emitter of the n-p-n bipolar transistor and a relatively heavily doped n-type surface region in the second n-type well for serving as the collector contact region of the n-p-n bipolar transistor; forming simultaneously a relatively heavily doped p-type region in the first p-type well for serving as the drain of the PMOS transistor, a relatively heavily doped p-type surface region in the first n-type well for serving as the source of the PMOS transistor, and a relatively heavily doped p-type surface region in the second p-type well for serving as the base contact region of the n-p-n bipolar transistor; and providing polysilicon gate electrodes to the PMOS and NMOS transistors.
Claim 6
Dependent Claim
39 words
The process of claim 3 in which the forming in the substrate of the first set of the relative)y lightly doped n-type wells utilizes a common donor ion implantation step through a mask apertured to define the three wells.
Claim 7
Dependent Claim
48 words
The process of claim 4 in which the forming, in the first and second well of the first set, of the first and second relatively lightly doped p-type wells utilizes a common acceptor ion implantation step through a mask apertured to define said first and second p-type wells.
Claim 8
Dependent Claim
42 words
The process of claim 5 in which the common donor ion implantation to form the first set of n-type wells is a phosphorus implantation and the common acceptor ion implantation to form the first and second p-type wells is a boron implantation.
Claim 9
Dependent Claim
55 words
The process of claim 5 in which the forming of the relatively heavily doped n-type surface regions utilizes a common pair of donor ion implantation steps through a mask apertured to define the source and drain of the NMOS transistor, the emitter of the n-p-n transistor and the collector contact region of the n-p-n transistor.
Claim 10
Dependent Claim
45 words
The process of claim 7 in which the forming of the relatively heavily doped p-type regions utilizes a common acceptor ion implantation through a mask apertured to define the source and drain of the PMOS transistor and the base contact region of the n-p-n transistor.
Claim 11
Dependent Claim
22 words
The process of claim 7 in which a common pair of donor ion implantation steps include common arsenic and phosphorus implantation steps.
Claim 12
Dependent Claim
46 words
The process of claim 9 in which the forming of the relatively heavily doped p-type regions utilizes a common boron ion implantation step through a mask apertured to define the source and drain of the PMOS transistor and the base contact region of the n-p-n transistor.
Claim 13
Dependent Claim
13 words
The process of claim 3 in which the semiconductive substrate is monocrystalline silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-16 | 1993-10-16 | 1994-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-16 | 1997-10-16 | 1998-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-16 | 2001-10-16 | 2002-04-17 | $7700.00 | Window Closed / Lapsed |