Method of forming a field plate in a high voltage array

Claim 1

In a semiconductor memory of the type having an array of electrically programmable memory cells arranged in rows and columns, each of said memory cells comprising a floating-gate transistor, and a row select transistor having a source-to-drain path connected between said floating-gate transistor and a column line and having a gate, wherein field oxide regions are disposed between adjacent memory cells in the same row, and wherein the gates of the row select transistors in each row are connected by way of a conducting row line to a driver associated with the row, said driver driving a voltage on said row line so that the floating-gate transistors in a selected row are connected to the associated column lines and so that the floating-gate transistors of the unselected rows are not connected to their associated column lines, the improvement comprising: an electrically isolated conductive layer disposed over said field oxide regions between adjacent memory cells, wherein a plurality of said row lines are overlying said electrically isolated conductive layer and are separated therefrom by a dielectric layer so that the voltage on each of said overlying row lines is capacitively coupled to said electrically isolated conductive layer.