Non-volatile memory device

Claim 2

In a floating gate storage device having first and second semiconductor regions spaced apart by a third region; said first and second regions forming the drain and source, respectively, of said device and said third region forming the channel region of said device; said floating gate device also having a first conductive floating gate member insulated from and overlying said channel region, and a second conductive control gate member insulated from and overlying at least a portion of said first gate, the improvement comprising: means for making the floating gate-to-source capacitance greater than the floating gate-to-drain capacitance wherein: (a) said channel region wraps around said drain region and closes upon itself; (b) said source region wraps around said channel region and closes upon itself; and (c) said first floating gate member overlies said channel region for the full length thereof and closes upon itself.

Claim 3

The floating gate storage device of claim 1 wherein the improvement further comprises the formation of said first, second and third regions within a body of semiconductor material located on an insulating substrate.

Claim 4

The floating gate storage device of claim 1 wherein the improvement further comprises a fourth region of semiconductive material surrounding said source region and closing upon itself and a third, field shield, conductive layer insulated from and overlying said fourth region and also closing upon itself; and wherein said first, second, third and fourth regions are formed within a body of semiconductor material located on an insulating substrate.

Claim 5

The floating gate storage device of claim 3 wherein said first and third regions are of one conductivity type and wherein said second and fourth regions are of opposite conductivity type.

Claim 6

The floating gate storage device of claim 4 further including: (a) a fifth region of said one conductivity type; (b) means for applying a potential to said fifth region; and (c) wherein said third conductive layer functions as the gate electrode of a field-effect transistor whose source and drain regions are said second and fifth region, said field-effect transistor when turned on coupling said potential to said second region.

Claim 7

The floating gate storage device of claim 1 wherein the perimeter of said drain region is less than the perimeter of said source region.

Claim 8

The combination as claimed in claim 1 wherein the improvement further comprises means for forming a first relatively thin high quality insulating layer completely surrounding said first floating gate member and a second relatively thick low quality insulating layer above said first high quality layer.

Claim 9

A solid state memory comprising: a body of semiconductor material predominantly of one conductivity type said body having a surface; a matrix array of memory cells, formed along one surface of said body arranged in rows and columns; each one of said cells comprised of a storage device (P S ) in series with a switching device (P W ), for selection, including: a field shield comprising a first frame-like structure including a layer of insulating material on said surface and a layer of conductive material on said layer of insulating material, said field shield having a closed geometry which encloses a first portion of said surface and separates said first portion of said surface from a second portion of said surface; a semiconductor device extending into said body in said first portion of said surface, said semiconductor device comprising: i. a second frame-like structure including a layer of insulating material on said first portion of said surface and a layer of conductive material on said layer of insulating material, said second frame-like structure having a closed geometry separating an outer portion of said first portion of said surface drom an inner portion of said first portion of said surface; said second frame-like structure defining the gate of said storage device; ii. a first region of opposite conductivity type to said body extending into said body from said inner portion of said first portion of said surface, said first region being surrounded by said second frame-like structure; said first region defining the drain region of said storage device; iii. a second region of opposite conductivity type to said body extending into said body from said outer portion of said first portion of said surface, said second region surrounding said second frame-like structure; said second region defining the source region of said storage device and the drain region of said switching device; a third region of opposite conductivity type to said body extending into said body surrounding said first frame like structure; said third region defining the drain region of said switching device and said first frame-like structure functioning as the gate of said switching device; said field shield of one device in a column being common to adjacent devices in that column and extending the length of a column, a field insulating layer overlying said frame-like structures, for insulating (floating) said second frame like structures; row conductors disposed above said field layer in a generally orthogonal direction to said columns, each row conductor overlying a row of memory cells and making contact to said first region via contact holes formed in insulating layers between a location on said first region at said surface of said body and said conductor; and a control gate disposed above said field layer and extending along said row conductors and overlying a portion of said second frame like structures.

Claim 10

A solid state memory comprising: a body of semiconductor material predominantly of one conductivity type said body having a surface; a matrix array of memory cells, formed along one surface of said body arranged in rows and columns; each one of said cells comprised of a storage device (P S ) in series with a switching device (P W ), for selection, including: a field shield comprising a first frame-like structure including a layer of insulating material on said surface and a layer of conductive material on said layer of insulating material, said field shield having a closed geometry which encloses a first portion of said surface and separates said first portion of said surface from a second portion of said surface; a semiconductor device extending into said body in said first portion of said surface, said semiconductor device comprising: i. a second frame-like structure including a layer of insulating material on said first portion of said surface and a layer of conductive material on said layer of insulating material, said second frame-like structure having a closed geometry separating an outer portion of said first portion of said surface drom an inner portion of said first portion of said surface; said second frame-like structure defining the gate of said storage device; ii. a first region of opposite conductivity type to said body extending into said body from said inner portion of said first portion of said surface, said first region being surrounded by said second frame-like structure; said first region defining the drain region of said storage device; iii. a second region of opposite conductivity type to said body extending into said body from said outer portion of said first portion of said surface, said second region surrounding said second frame-like structure; said second region defining the source region of said storage device and the drain region of said switching device; a third region of opposite conductivity type to said body extending into said body surrounding said first frame like structure; said third region defining the drain region of said switching device and said first frame-like structure functioning as the gate of said switching device; said field shield of one device in a column being common to adjacent devices in that column and extending the length of a column, a field insulating layer overlying said frame-like structures, for insulating (floating) said second frame like structures; row conductors disposed above said field layer in a generally orthogonal direction to said columns, each row conductor overlying a row of memory cells and making contact to said first region via contact holes formed in insulating layers between a location on said first region at said surface of said body and said conductor; and a control gate disposed above said field layer and extending along said row conductors and overlying a portion of said second frame like structures.

Claim 11

The combination as claimed in claim 8 further including an insulating substrate, and wherein said body of semiconductor material is grown on said substrate.

Claim 12

A floating gate field effect device comprising: (a) a body of semiconductor material predominantely of one conductivity type, said body having a surface; (b) a floating gate comprising a first frame-like structure including a layer of insulating material on said surface and a layer of conductive material on said layer of insulating material, said floating gate having a closed geometry which encloses a first inner portion of said surface and separates said first portion of said surface from a second outer portion of said surface; (c) a first region of opposite conductivity type to said body extending into said body from said first inner portion of said surface, said first region being surrounded by said first frame-like structure; (d) a second region of opposite conductivity type to said body extending into said body from said second outer portion of said surface, said second region surrounding said first frame-like structure. (e) a field shield comprising a second frame-like structure including a layer of insulating material on said surface and a layer of conductive material on said layer of insulating material surrounding at said surface said second region. (f) a relatively thick insulating layer completely surrounding said floating gate and said field shield; and (g) a layer of conductive material on top of said thick insulating layer overlying at least a portion of said floating gate.

Claim 13

A floating gate field effect device comprising: (a) a body of semiconductor material predominantely of one conductivity type, said body having a surface; (b) a floating gate comprising a first frame-like structure including a layer of insulating material on said surface and a layer of conductive material on said layer of insulating material, said floating gate having a closed geometry which encloses a first inner portion of said surface and separates said first portion of said surface from a second outer portion of said surface; (c) a first region of opposite conductivity type to said body extending into said body from said first inner portion of said surface, said first region being surrounded by said first frame-like structure; (d) a second region of opposite conductivity type to said body extending into said body from said second outer portion of said surface, said second region surrounding said first frame-like structure. (e) a field shield comprising a second frame-like structure including a layer of insulating material on said surface and a layer of conductive material on said layer of insulating material surrounding at said surface said second region. (f) a relatively thick insulating layer completely surrounding said floating gate and said field shield; and (g) a layer of conductive material on top of said thick insulating layer overlying at least a portion of said floating gate.

Claim 14

The field-effect device as claimed in claim 10 further including an insulating substrate and wherein said semiconductor body is formed on said substrate.

Claim 15

The combination as claimed in claim 11 wherein a third region is formed within said body between said first and second regions isolated from and below said first frame like structure, surrounding said first region and defining the conduction channel of said floating gate field effect device.