US4764482A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating an integrated circuit containing bipolar and MOS transistors
Assignee: Intersil Corp
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Filing: 1987-11-23
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Granted: 1988-08-16
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Expires: 2007-11-23
Abstract
Abstract A method for fabricating an integrated circuit including at least one metal-oxide-semiconductor transistor (MOS) and at least one bipolar transistor is disclosed. The pocket regions used to reduce the short channel effect in the MOS transistor are formed simultaneously with the base region for the bipolar transistor.
Inventors
- 👤 Sheng T. Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:16
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
247 words
A method of fabricating an integrated circuit including at least one complementary metal-oxide-semiconductor device and at least one bipolar transistor in the same semiconductor substrate of a first conductivity type, comprising the steps of: (a) forming a plurality of spaced regions of a second conductivity type adjacent a surface of the semiconductor substrate, thereby defining at least one region of a first conductivity type therebetween; (b) simultaneously forming pocket regions in the region of a first conductivity type, for receiving device regions where a metal-oxide-semiconductor device having a channel region of a first conductivity type is to be located, and a base region in the region of a second conductivity type where a bipolar transistor is to be located, said base region being of a first conductivity type; (c) forming pocket regions in a region of a second conductivity type, for receiving device regions where a metal-oxide-semiconductor device having a channel region of a second conductivity type is to be located; (d) simultaneously forming source and drain device regions for the metal-oxide-semiconductor device having a channel region of a first conductivity type and an emitter region and a collector contact doped region for the bipolar transistor to be located in the region of a second conductivity type; and (e) simultaneously forming source and drain device regions for the metal-oxide-semiconductor device having a channel region of the second conductivity type and a base contact region for the bipolar transistor located in the region of a second conductivity type.
Claim 2
Independent Claim
247 words
A method of fabricating an integrated circuit including at least one complementary metal-oxide-semiconductor device and at least one bipolar transistor in the same semiconductor substrate of a first conductivity type, comprising the steps of: (a) forming a plurality of spaced regions of a second conductivity type adjacent a surface of the semiconductor substrate, thereby defining at least one region of a first conductivity type therebetween; (b) simultaneously forming pocket regions in the region of a first conductivity type, for receiving device regions where a metal-oxide-semiconductor device having a channel region of a first conductivity type is to be located, and a base region in the region of a second conductivity type where a bipolar transistor is to be located, said base region being of a first conductivity type; (c) forming pocket regions in a region of a second conductivity type, for receiving device regions where a metal-oxide-semiconductor device having a channel region of a second conductivity type is to be located; (d) simultaneously forming source and drain device regions for the metal-oxide-semiconductor device having a channel region of a first conductivity type and an emitter region and a collector contact doped region for the bipolar transistor to be located in the region of a second conductivity type; and (e) simultaneously forming source and drain device regions for the metal-oxide-semiconductor device having a channel region of the second conductivity type and a base contact region for the bipolar transistor located in the region of a second conductivity type.
Claim 3
Dependent Claim
61 words
A method of fabricating an integrated circuit according to claim 1, further comprising the steps of: forming before step (b) a gate oxide on at least the areas which overlie the regions where the metal-oxide-semiconductor devices are to be located; and then forming gate electrodes on the gate oxide which overlies the regions where the metal-oxide-semiconductor devices are to be located.
Claim 4
Dependent Claim
56 words
A method of fabricating an integrated circuit according to claim 2, further comprising the steps of: simultaneously forming before step (d) a spacer oxide on the sidewalls of said gate electrodes and an oxide layer over said substrate between the areas where the emitter, base contact and collector contact will be located for the bipolar transistor.
Claim 5
Dependent Claim
45 words
A method of fabricating an integrated circuit according to claim 1, further comprising the step of: forming after step (a) a collector region of a first conductivity type in a region of a second conductivity type where an additional bipolar transistor is to be located.
Claim 6
Dependent Claim
82 words
A method of fabricating an integrated circuit according to claim 4, further comprising the steps of: during step (c) simultaneously forming in the collector region of a first conductivity type a base region for the additional bipolar transistor, said base region for the additional bipolar transistor being of a second conductivity type; during step (d) simultaneously forming a base contact for the additional bipolar transistor; and during step (e) simultaneously forming the emitter region and collector contact for the additional bipolar transistor.
Claim 7
Dependent Claim
80 words
A method of fabricating an integrated circuit according to claim 1, further comprising the steps of: forming a heavily doped buried collector of a second conductivity type in said region of a second conductivity type where said at least one bipolar transistor is to be formed using a first ion implantation technique; and connecting said buried collector to the surface of said substrate by forming a heavily doped region of a second conductivity type using a second ion implantation technique.
Claim 8
Dependent Claim
29 words
A method of fabricating an integrated circuit according to claim 6 wherein said plurality of regions of first and second conductivity types are formed using a retrograde doping process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-16 | 1992-02-15 | 1992-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-16 | 1996-02-15 | 1996-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-16 | 2000-02-15 | 2000-08-16 | $7700.00 | Window Closed / Lapsed |