US4280855A
Expired / Lapsed
US
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Method of making a dual DMOS device by ion implantation and diffusion
Assignee: International Business Machines Corp
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Filing: 1980-01-23
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Granted: 1981-07-28
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Expires: 2000-01-23
Abstract
Abstract A diffused MOS (DMOS) device and method for making same are disclosed. The prior art DMOS device is improved upon by ion implanting a depletion extension L D to the drain. However, the introduction of the depletion extension L D introduces a manufacturing statistical variation in the characteristics of the resultant devices so produced. The problem of the effects of the variations in the length L D and thus, variations in the resulting transconductance of the device, is solved by placing two of these devices in parallel. When one device has its L D relatively shorter, the companion device will also have its L D correspondingly longer. The method of producing the dual devices is by ion implanting a single conductivity region which forms the L D for both the left- and right-hand channels for the left- and right-hand DMOS structures. If the mask for the ion-implanted region is misaligned slightly to the right, then the effective L D for the right-hand channel is somewhat longer but the effective L D for the left-hand channel is correspondingly shorter, so that the net parallel transconductance for the two devices remains the same as the transconductance for a perfectly symmetric ion-implanted region.
Inventors
- 👤 Claude L. Bertin
- 👤 Francisco H. De La Moneda
- 👤 Donald A. Soderman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:58
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/60; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10P30/21; H10P30/212
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
296 words
A method for forming a pair of mutually compensated diffused MOS devices having a predictable transconductance, comprising the steps of: simultaneously forming a first and second channel regions of a first conductivity type in a semiconductor substrate of said first conductivity type, separated by a first distance; simultaneously forming a first and second source regions of a second conductivity type within said first and second channel regions of said first conductivity type; forming a third drain region of said second conductivity type between said first and second channel regions of said first conductivity type, having a first separation distance from said first channel region of said first conductivity type and a second separation distance from said second channel region of said first conductivity type, for a common drain of two FET devices having said first and second regions of said second conductivity type as the respective sources of said two FET devices; ion implanting a conductivity layer of said second conductivity type in said substrate over said third drain region of said second conductivity type, which extends into said region separating said third drain region of said second conductivity type from said first channel region of said first conductivity type and which extends into said region separating said third drain region of said second conductivity type from said second channel region of said first conductivity type; simultaneously depositing a first gate electrode over the region separating said third drain region and said first source region and a second gate electrode over the region separating said third drain region and said second source region; whereby a parallel connected pair of FET devices is formed wherein the transconductance of the first FET device compensates for the error due to misalignment, in the transconductance of the second FET device.
Claim 2
Independent Claim
296 words
A method for forming a pair of mutually compensated diffused MOS devices having a predictable transconductance, comprising the steps of: simultaneously forming a first and second channel regions of a first conductivity type in a semiconductor substrate of said first conductivity type, separated by a first distance; simultaneously forming a first and second source regions of a second conductivity type within said first and second channel regions of said first conductivity type; forming a third drain region of said second conductivity type between said first and second channel regions of said first conductivity type, having a first separation distance from said first channel region of said first conductivity type and a second separation distance from said second channel region of said first conductivity type, for a common drain of two FET devices having said first and second regions of said second conductivity type as the respective sources of said two FET devices; ion implanting a conductivity layer of said second conductivity type in said substrate over said third drain region of said second conductivity type, which extends into said region separating said third drain region of said second conductivity type from said first channel region of said first conductivity type and which extends into said region separating said third drain region of said second conductivity type from said second channel region of said first conductivity type; simultaneously depositing a first gate electrode over the region separating said third drain region and said first source region and a second gate electrode over the region separating said third drain region and said second source region; whereby a parallel connected pair of FET devices is formed wherein the transconductance of the first FET device compensates for the error due to misalignment, in the transconductance of the second FET device.
Claim 3
Dependent Claim
36 words
The method of claim 1 which further comprises: said first and second regions of said first conductivity type being diffused dopant regions; said first and second regions of said second conductivity type being diffused dopant regions.
Claim 4
Dependent Claim
21 words
The method of claim 2 wherein said first conductivity type is P-type conductivity and said second conductivity type is N-type conductivity.
Claim 5
Dependent Claim
21 words
The method of claim 2 wherein said first conductivity type is N-type conductivity and said second conductivity type is P-type conductivity.
Claim 6
Dependent Claim
33 words
The method of claim 1, wherein said first and second regions of said first conductivity type are ion-implanted regions; and said first and second regions of said second conductivity type are ion-implanted regions.
Claim 7
Dependent Claim
21 words
The method of claim 5 wherein said first conductivity type is P-type conductivity and said second conductivity type is N-type conductivity.
Claim 8
Dependent Claim
21 words
The method of claim 5 wherein said first conductivity type is N-type conductivity and said second conductivity type is P-type conductivity.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-07-27 | 1985-01-26 | 1985-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-07-27 | 1989-01-26 | 1989-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-07-27 | 1993-01-26 | 1993-07-28 | $7700.00 | Window Closed / Lapsed |