Method of manufacturing field effect transistors of the MOS-type

Claim 1

A method of manufacturing field-effect transistor of the MOS-type in one principal surface of a substrate of monocrystalline semiconductor material having a first conductivity type, comprising on the one hand two regions having a second conductivity type opposite to the first, namely a source region and a drain region, respectively, terminating at said surface and separated from one another by an intermediate channel region of the substrate and, on the other hand, a control gate of an electrically conductive material extending above said intermediate region, from which it is insulated by a layer of dielectric material, said method comprising the following steps: forming a masking layer of silica on the principal surface of the substrate (1) and forming two openings to expose two zones; diffusing impurities having the second conductivity type through these openings to form a source region (8) and a drain region (9); removing that portion of the masking silica layer which is present on said intermediate region (12) and forming, by successive deposits over the entire principal surface, a layer (70) of doped silica containing a doping impurity of the second conductivity type, the doping level decreasing with each successive deposit; removing said layer of doped silica by chemical etching except for two portions situated on the intermediate region respectively adjacent the source and drain regions, said portions decreasing in section in the direction toward said substrate to form a pit; diffusing impurities into the substrate from said two portions by heating to a temperature of from 950° C. to 1150° C. to form therein two regions (43) and (44) defining the ends of the channel; forming a layer of dielectric material (45) on the exposed zones of the principal surface during or after this diffusion; forming a layer (50) of conductive metal over the entire principal surface, said layer having reductions in thickness around said portions; and removing those portions of said metal layer which are situated above the portions of the layer of doped silica present on said two defining regions (43) and (44) by chemical etching to form source, gate and drain contacts (71), (72), and (73), respectively.

Claim 2

A method of manufacturing field-effect transistor of the MOS-type in one principal surface of a substrate of monocrystalline semiconductor material having a first conductivity type, comprising on the one hand two regions having a second conductivity type opposite to the first, namely a source region and a drain region, respectively, terminating at said surface and separated from one another by an intermediate channel region of the substrate and, on the other hand, a control gate of an electrically conductive material extending above said intermediate region, from which it is insulated by a layer of dielectric material, said method comprising the following steps: forming a masking layer of silica on the principal surface of the substrate (1) and forming two openings to expose two zones; diffusing impurities having the second conductivity type through these openings to form a source region (8) and a drain region (9); removing that portion of the masking silica layer which is present on said intermediate region (12) and forming, by successive deposits over the entire principal surface, a layer (70) of doped silica containing a doping impurity of the second conductivity type, the doping level decreasing with each successive deposit; removing said layer of doped silica by chemical etching except for two portions situated on the intermediate region respectively adjacent the source and drain regions, said portions decreasing in section in the direction toward said substrate to form a pit; diffusing impurities into the substrate from said two portions by heating to a temperature of from 950° C. to 1150° C. to form therein two regions (43) and (44) defining the ends of the channel; forming a layer of dielectric material (45) on the exposed zones of the principal surface during or after this diffusion; forming a layer (50) of conductive metal over the entire principal surface, said layer having reductions in thickness around said portions; and removing those portions of said metal layer which are situated above the portions of the layer of doped silica present on said two defining regions (43) and (44) by chemical etching to form source, gate and drain contacts (71), (72), and (73), respectively.