Method of making junction isolated bipolar device in unisolated IGFET IC

Claim 2

A process of fabricating an integrated circuit including complementary insulated gate field effect transistors and a junction isolated bipolar device comprising: diffusing first P type impurities into an N conducting type substrate to form a first P type region; epitaxially forming an N type layer on said substrate; implanting second P type impurities in the surface of said epitaxial layer to form a second P type region; diffusing said first P type region up and said second P type region down into said epitaxial layer until they overlap to isolate a third N-type region of said epitaxial layer from the remainder of the epitaxial layer; diffusing first N type impurities into said second P type region to form source and drain regions of an N channel device and into said third N type region to form a first region of said bipolar device; and diffusing third P type impurities into said epitaxial layer to form source and drain regions of a P channel device and into said third N type region to form a second region of said bipolar device.

Claim 3

The process according to claim 1 wherein said first P type impurities are introduced into said substrate through a mask; and including introducing second N type impurities into said first region through said mask after diffusion of said first P type impurities.

Claim 4

The process according to claim 2 wherein said implanting said second P type impurities includes forming a fourth P type region in the surface of said epitaxial layer which will be said third N type region, said fourth P type region being the base of said bipolar device, said first region of said bipolar device being the emitter and said second region of said bipolar device being the base contact.

Claim 5

The process according to claim 2 wherein said first region of said bipolar device forms the contact region of the base of a lateral bipolar device, said third N type region forms the base of said bipolar device, and said third P type diffusion forms laterally spaced collector and emitter regions in said third N type region.

Claim 6

A process for fabricating an integrated circuit comprising: diffusing P+ type impurities into an N type substrate to form a buried P+ region; epitaxially forming an N- type layer on said substrate; introducing P- impurities into the surface of said epitaxially layer to form a P- surface region; diffusing said P+ and P- regions into said epitaxial layer until they overlap to form an isolated N- region of said epitaxial layer; diffusing N+ impurities into said surface P- region to form source and drain regions of an N channel device and into said isolated N- region to form a region of a bipolar device; and diffusing P+ type impurities into said epitaxial layer to form source and drain regions of a P channel device and into said isolated N- region to form another region of said bipolar device.

Claim 7

A process for fabricating an integrated circuit comprising: diffusing P+ type impurities into an N type substrate to form a buried P+ region; epitaxially forming an N- type layer on said substrate; introducing P- impurities into the surface of said epitaxially layer to form a P- surface region; diffusing said P+ and P- regions into said epitaxial layer until they overlap to form an isolated N- region of said epitaxial layer; diffusing N+ impurities into said surface P- region to form source and drain regions of an N channel device and into said isolated N- region to form a region of a bipolar device; and diffusing P+ type impurities into said epitaxial layer to form source and drain regions of a P channel device and into said isolated N- region to form another region of said bipolar device.

Claim 8

The processing according to claim 5 wherein introducing P- impurities also forms a P- region in the surface of said epitaxial layer which will be said isolated N- region spaced from the other P- impurity regions.

Claim 9

The process according to claim 5 wherein said first mentioned P+ type impurities are introduced through a mask and including introducing N+ type impurities through said mask after diffusion of said P+ type impurities.

Claim 10

A process for fabricating an integrated circuit including complementary insulated gate field effect and bipolar transistors comprising: diffusing first P type impurities into an N type substrate to form a buried region; diffusing first N type impurities into said P buried region to form an N buried region; epitaxially forming an N type layer on said substrate; introducing second P type impurities into the surface of said epitaxial layer at the edges of said P buried region to form a first P surface region and above said N buried region to form a second P surface region; diffusing said impurities into said N epitaxial layer until said first P surface region overlaps said P buried region to form an isolated N region; diffusing second N type impurities into said first P surface region to form source and drain region, into said second P surface region to form an emitter region, and into said isolated N region to form a collector contact region; and diffusing third P type impurities into said N epitaxial region to form source and drain regions, into said first P surface region to form an isolation and N channel body contact region, and into said second P surface region to form a base contact region.

Claim 11

A process for fabricating an integrated circuit including complementary insulated gate field effect and bipolar transistors comprising: diffusing first P type impurities into an N type substrate to form a buried region; diffusing first N type impurities into said P buried region to form an N buried region; epitaxially forming an N type layer on said substrate; introducing second P type impurities into the surface of said epitaxial layer at the edges of said P buried region to form a first P surface region and above said N buried region to form a second P surface region; diffusing said impurities into said N epitaxial layer until said first P surface region overlaps said P buried region to form an isolated N region; diffusing second N type impurities into said first P surface region to form source and drain region, into said second P surface region to form an emitter region, and into said isolated N region to form a collector contact region; and diffusing third P type impurities into said N epitaxial region to form source and drain regions, into said first P surface region to form an isolation and N channel body contact region, and into said second P surface region to form a base contact region.

Claim 12

The process according to claim 8 wherein said first P type impurities to form said P buried region are introduced through a mask and said first N type impurities to form said N buried region are introduced through said mask after diffusion of said first P type impurities.

Claim 13

The process according to claim 8 wherein said second P type impurities are introduced to form a base region in said epitaxial layer which is a collector region, said second N type impurities are diffused in said base region to form an emitter region, and said third P type impurities are diffused in said base region to form a base contact.