US4027324A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bidirectional transistor
Assignee: Sony Corp
•
Filing: 1976-01-21
•
Granted: 1977-05-31
•
Expires: 1996-01-21
Abstract
Abstract This invention relates to a bidirectional transistor, and particularly to a transistor having two low impurity concentration regions on either side of a base region which act as the emitter or collector regions with a minority carrier diffusion length L substantially greater than the width of such emitter and collector regions when operating in either direction. High impurity concentration regions interface with the low impurity concentration regions to provide a built-in-field which is larger than kT/(qL) and which make the drift current produced by the built-in-field substantially balance the minority carrier diffusion current injected from the base region. The built-in-field is preferably larger than 10 3 V/cm, and the potential barrier across is preferably larger than 0.1 eV. Two of the high impurity concentration regions provide first and second L-H junctions. A third L-H junction surrounds one of the low impurity concentration regions. This third L-H junction greatly improves the bidirectional characteristics of the device.
Inventors
- 👤 Hajime Yagi
- 👤 Tadaharu Tsuyuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:23
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/40; H10D10/461; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D62/137; H10D84/00; H10D84/60; H10D84/67; H10D84/673
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
305 words
A semiconductor device comprising: (a) a semiconductor substrate having a major surface; (b) a first semiconductor region of one conductivity type; (c) a second semiconductor region of the opposite conductivity type facing said surface, surrounding said first region forming a first PN junction therewith; (d) a third semiconductor region of said one conductivity type surrounding said second region forming a second PN junction therewith; (e) said first region having a first lightly doped portion adjacent to said first PN junction and a first heavily doped portion facing said surface and forming a third junction between said first lightly and first heavily doped portions; f. said third junction being located from said first PN junction by a distance whose greatest distance in a perpendicular direction at any point in said first PN junction is less than the diffusion length L 1 of minority carriers in said lightly doped portion and having an electric field at said third junction which is larger than 10 3 V/cm. g. said third region having a second lightly doped portion adjacent to said second PN junction and a second heavily doped portion facing said surface, surrounding said lightly doped portion and forming a fourth junction between said second lightly and second heavily doped portions; (h) said fourth junction being located from said second PN junction by a distance whose greatest distance in a perpendicular direction at any point in said second PN junction is less than the diffusion length L 2 of minority carriers in said lightly doped portion and having an electric field at said fourth junction which is larger than 10 3 V/cm, and (i) biasing means for transporting majority carriers in said first region to said third region in a first period and transporting majority carriers in said third region to said first region in a second period.
Claim 2
Dependent Claim
305 words
A semiconductor device comprising: (a) a semiconductor substrate having a major surface; (b) a first semiconductor region of one conductivity type; (c) a second semiconductor region of the opposite conductivity type facing said surface, surrounding said first region forming a first PN junction therewith; (d) a third semiconductor region of said one conductivity type surrounding said second region forming a second PN junction therewith; (e) said first region having a first lightly doped portion adjacent to said first PN junction and a first heavily doped portion facing said surface and forming a third junction between said first lightly and first heavily doped portions; f. said third junction being located from said first PN junction by a distance whose greatest distance in a perpendicular direction at any point in said first PN junction is less than the diffusion length L 1 of minority carriers in said lightly doped portion and having an electric field at said third junction which is larger than 10 3 V/cm. g. said third region having a second lightly doped portion adjacent to said second PN junction and a second heavily doped portion facing said surface, surrounding said lightly doped portion and forming a fourth junction between said second lightly and second heavily doped portions; (h) said fourth junction being located from said second PN junction by a distance whose greatest distance in a perpendicular direction at any point in said second PN junction is less than the diffusion length L 2 of minority carriers in said lightly doped portion and having an electric field at said fourth junction which is larger than 10 3 V/cm, and (i) biasing means for transporting majority carriers in said first region to said third region in a first period and transporting majority carriers in said third region to said first region in a second period.
Claim 3
Dependent Claim
22 words
A semiconductor device according to claim 1, in which said second heavily doped portion has a portion extended inwardly along said surface.
Claim 4
Dependent Claim
23 words
A semiconductor device according to claim 1 in which the potential barriers at said third and fourth junctions is larger than 0.1 eV.
Claim 5
Dependent Claim
41 words
A semiconductor device according to claim 1 in which said electric field at said third and fourth junctions is larger than kT/(qL) where k is the Bolzmann constant, T is the temperature and q is the charge of the minority carrier.
Claim 6
Dependent Claim
41 words
A semiconductor device according to claim 1 in which said second region includes a layer portion lying parallel to said major surface and a ring-like portion rising from said layer portion to said major surface, said ring-like portion being highly doped.
Claim 7
Dependent Claim
43 words
A semiconductor device according to claim 5 in which said second heavily doped portion of said third region includes a layer portion lying parallel to said major surface and a ring-like portion rising from said second heavily doped portion to said major surface.
Claim 8
Dependent Claim
34 words
A semiconductor device according to claim 6 in which said layer portion of said second region extends laterally into contact with said ring-like portion of said second heavily doped portion of said third region.
References Cited (Backward Citations)
GB906036A
Cited
FR2130399A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-30 | 1980-11-29 | 1981-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-30 | 1984-11-29 | 1985-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-30 | 1988-11-29 | 1989-05-31 | $7700.00 | Window Closed / Lapsed |