Fabrication of bipolar/CMOS integrated circuits

Claim 1

A method for fabricating an integrated circuit including complementary MOS transistors and an NPN-type bipolar transistor, comprising the steps of: forming an N-type epitaxial layer on a P-type substrate, a buried layer being provided at least at a location of the bipolar transistor, forming a thick oxide layer at locations other than locations of wells of the MOS transistors, of a collector well region of the bipolar transistor and of a base-emitter region of the bipolar transistor, forming the wells of the MOS transistors and the collector well of the bipolar transistor, forming the insulated gates, the spacers and sources and drains of the MOS transistors, covering the entire structure, including the insulated gates, the thick oxide layer and the spacers, with a protection layer including a first layer of silicon oxide and a first layer of silicon nitride, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon or amorphous silicon and a second layer of encapsulation oxide, opening these last two layers at a center of the emitter-base region of the bipolar transistor, diffusing the dopant contained in the first silicon layer into the underlying epitaxial layer, to form the extrinsic base of the bipolar transistor, implanting an N-type collector dopant, implanting a P-type dopant to form an intrinsic base of the bipolar transistor, depositing a second silicon nitride layer, depositing a second layer of polysilicon, anisotropically etching the second polysilicon layer to leave in place spacers in the vertical portions thereof, and removing the silicon nitride, depositing a third N-type doped polysilicon layer and diffusing the dopant to form the emitter of the bipolar transistor, performing a silicidation, depositing a planarized insulating layer, and performing the metallizations.

Claim 2

A method for fabricating an integrated circuit including complementary MOS transistors and an NPN-type bipolar transistor, comprising the steps of: forming an N-type epitaxial layer on a P-type substrate, a buried layer being provided at least at a location of the bipolar transistor, forming a thick oxide layer at locations other than locations of wells of the MOS transistors, of a collector well region of the bipolar transistor and of a base-emitter region of the bipolar transistor, forming the wells of the MOS transistors and the collector well of the bipolar transistor, forming the insulated gates, the spacers and sources and drains of the MOS transistors, covering the entire structure, including the insulated gates, the thick oxide layer and the spacers, with a protection layer including a first layer of silicon oxide and a first layer of silicon nitride, opening the protection layer at the base-emitter location of the bipolar transistor, forming a first P-type doped layer of polysilicon or amorphous silicon and a second layer of encapsulation oxide, opening these last two layers at a center of the emitter-base region of the bipolar transistor, diffusing the dopant contained in the first silicon layer into the underlying epitaxial layer, to form the extrinsic base of the bipolar transistor, implanting an N-type collector dopant, implanting a P-type dopant to form an intrinsic base of the bipolar transistor, depositing a second silicon nitride layer, depositing a second layer of polysilicon, anisotropically etching the second polysilicon layer to leave in place spacers in the vertical portions thereof, and removing the silicon nitride, depositing a third N-type doped polysilicon layer and diffusing the dopant to form the emitter of the bipolar transistor, performing a silicidation, depositing a planarized insulating layer, and performing the metallizations.