BiCMOS semiconductor memory device using load transistors formed on an insulating film

Claim 1

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a plurality of memory cells of a static random access memory each of which includes first and second driver MISFETs, and first and second load MISFETs, wherein each of said first and second driver MISFETs has a gate insulating film formed on said main surface, a gate electrode formed on said gate insulating film, and source and drain regions formed in said semiconductor substrate; peripheral circuits including an npn-type bipolar transistor, wherein said npn-type bipolar transistor comprises an emitter region of n-type conductivity formed in said semiconductor substrate, and a base region of p-type conductivity formed in said semiconductor substrate so as to surround said emitter region; a first insulating film formed over said gate electrodes of said driver MISFETs and over said main surface so as to cover said main surface; a base lead-out layer of said npn-type bipolar transistor electrically connected to said base region and formed on said first insulating film; first semiconductor strips formed on said first insulating film, wherein source, drain and channel forming regions of said load MISFETs are formed in said first semiconductor strips, wherein said drain region of said first load MISFET is electrically connected to said drain region of said first driver MISFET and to said gate electrode of said second driver MISFET, wherein said drain region of said second load MISFETs is electrically connected to said drain region of said second driver MISFET and to said gate electrode of said first driver MISFET, wherein said first semiconductor strips and base lead-out layer are comprised by the same level layer of a polycrystalline silicon film, wherein said source and drain regions of said load MISFETs, and said base lead-out layer are p-type conductivity; first conductive layers selectively formed on said polycrystalline silicon film in such a manner that said first conductive layers are formed on said source and drain regions of said load MISFETs and on said base lead-out layer and in such a manner that said first conductive layers are not formed on said channel forming regions of said load MISFETs, wherein said first conductive layers have a resistance value smaller than that of said polycrystalline silicon film; a second insulating film formed over said first conductive layers so as to cover a portion of said main surface, said second insulating film having an opening; and a second conductive layer formed over said second insulating film and electrically connected to said first conductive layer through said opening in said second insulating film.