US5015594A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of making BiCMOS devices having closely spaced device regions
Assignee: International Business Machines Corp
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Filing: 1988-10-24
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Granted: 1991-05-14
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Expires: 2008-10-24
Abstract
Abstract A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.
Inventors
- 👤 Shao-Fu S. Chu
- 👤 San-Mei Ku
- 👤 Russell C. Lange
- 👤 Joseph F. Shephard
- 👤 Paul J. Tsang
- 👤 Wen-Yuan Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:17
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/009
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
325 words
A method of forming at least one bipolar and two complementary metal oxide semiconductor transistors (BICMOS) comprising the steps of: providing a body of semiconductor material including first, second, and third electrically isolated device regions, said first and second device regions adjacent each other and of opposite conductivity types; forming first, second, and third studs over said first, second and third device regions, respectively, such that said first and second studs bisect said first and second device regions; using said first and second studs as masks to form first and second doped regions adjoining opposite sides of said first and second studs in each of said first and second device regions, respectively, each of said first and second doped regions of opposite conductivity type to its associated device region; forming first, second, and third insulating sidewalls on said first, second, and third studs, respectively; forming a layer of conductive material generally conformally over said semiconductor body, said studs, and said sidewalls to a depth at least equal to the height of said sidewalls; planarizing by chemically-mechanically polishing said layer of conductive material to a height generally equal to or less than the height of said sidewalls; and patterning the planarized layer of conductive material, whereby to form spaced apart first and second contacts overlying said first and second doped regions in each of said first and second device regions, respectively, and an extrinsic base contact overlying said third device region; removing said third stud while leaving the sidewall associated with said third stud to expose a portion of said third device region; using said third sidewall as a mask to form, by out-diffusion from a solid dopant source, an intrinsic base region of opposite conductivity type to said third device region in the surface of said third device region; and forming a vertical bipolar transistor in said third device region and first and second insulated gate transistors in said first and second device regions, respectively.
Claim 2
Independent Claim
325 words
A method of forming at least one bipolar and two complementary metal oxide semiconductor transistors (BICMOS) comprising the steps of: providing a body of semiconductor material including first, second, and third electrically isolated device regions, said first and second device regions adjacent each other and of opposite conductivity types; forming first, second, and third studs over said first, second and third device regions, respectively, such that said first and second studs bisect said first and second device regions; using said first and second studs as masks to form first and second doped regions adjoining opposite sides of said first and second studs in each of said first and second device regions, respectively, each of said first and second doped regions of opposite conductivity type to its associated device region; forming first, second, and third insulating sidewalls on said first, second, and third studs, respectively; forming a layer of conductive material generally conformally over said semiconductor body, said studs, and said sidewalls to a depth at least equal to the height of said sidewalls; planarizing by chemically-mechanically polishing said layer of conductive material to a height generally equal to or less than the height of said sidewalls; and patterning the planarized layer of conductive material, whereby to form spaced apart first and second contacts overlying said first and second doped regions in each of said first and second device regions, respectively, and an extrinsic base contact overlying said third device region; removing said third stud while leaving the sidewall associated with said third stud to expose a portion of said third device region; using said third sidewall as a mask to form, by out-diffusion from a solid dopant source, an intrinsic base region of opposite conductivity type to said third device region in the surface of said third device region; and forming a vertical bipolar transistor in said third device region and first and second insulated gate transistors in said first and second device regions, respectively.
Claim 3
Dependent Claim
45 words
A method in accordance with claim 1 and further including the step of using said third stud as a mask to form an extrinsic base link-up region of opposite conductivity type to said third device region adjoining said third stud in said third device region.
Claim 4
Dependent Claim
39 words
A method in accordance with claim 2 and further including the steps of annealing said body of semiconductor material to drive dopant from said layer of conductive material into said link-up region whereby to complete an extrinsic base region.
Claim 5
Dependent Claim
81 words
A method in accordance with claim 2 wherein said step of using said studs as masks to form said first and second doped regions and aid extrinsic base link-up region includes the steps of: masking a selected one of said device regions while depositing dopant impurities into the unmasked device regions; removing the mask from the selected one of said device regions; and masking the remaining two device regions while depositing dopant impurities into the selected one of said device regions.
Claim 6
Dependent Claim
23 words
A method in accordance with claim 1 wherein said layer of conductive material comprises a doped polysilicon, a polycide, or a refractory metal.
Claim 7
Dependent Claim
40 words
A method in accordance with claim 1 and further including the step of using said third sidewall as a mask to form a third doped region of same conductivity type as said third device region in said intrinsic base region.
Claim 8
Dependent Claim
66 words
A method in accordance with claim 1 wherein said step of forming said studs includes the steps of: forming a first layer of insulating material generally conformally over said semiconductor body; forming a second layer of conducting material over said first layer; forming a third layer of material over said second layer; and removing portions of said first, second, and third layers to delineate said studs.
Claim 9
Dependent Claim
34 words
A method in accordance with claim 7 wherein: said first layer comprises an oxide; said second layer comprises a doped polysilicon, a refractory metal, or a polycide; and said third layer comprises a nitride.
Claim 10
Dependent Claim
40 words
A method in accordance with claim 7 and further including the step of removing said third layer of material in each of said first and second studs whereby to form an electrical connection to said second layer of conductive material.
Claim 11
Dependent Claim
45 words
A method in accordance with claim 1 wherein said step of forming said sidewalls includes the steps of: forming a layer of insulating material generally conformally over said semiconductor body and said studs; and anisotropically etching said layer of insulating material to form said studs.
Claim 12
Dependent Claim
26 words
A method in accordance with claim 1 and further including the step of forming an electrical contact on the exposed portion of said third doped region.
Claim 13
Dependent Claim
36 words
A method in accordance with claim 1 and further including the step of using said third sidewall as a mask to form a buried implant region of said first conductivity type in said third device region.
Claim 14
Dependent Claim
60 words
A method in accordance with claim 1 and further including the steps of: forming a fourth doped region of said first conductivity type underneath said first doped region; and forming a reachthrough region of said first conductivity type extending from the surface of said semiconductor body to said fourth doped region, said reachthrough region insulated from said extrinsic base region.
Claim 15
Dependent Claim
17 words
A method in accordance with claim 1 wherein said body of semiconductor material comprises silicon semiconductor material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-13 | 1994-11-12 | 1995-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-13 | 1998-11-12 | 1999-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-13 | 2002-11-12 | 2003-05-14 | $7700.00 | Window Closed / Lapsed |