Integrated digital multiplier circuit using current mode logic

Claim 2

For use in a monolithic integrated multiplier circuit, the combination of: a plurality of NPN transistors and resistors fabricated in accordance with a high-density triple diffusion process allowing for use of a two-micron minimum geometry, and correspondingly small junction depths, to provide a very high packing density and a corresponding low defect rate and low production cost; and circuit means for connecting said transistors and resistors to operate in current mode logic, to provide a circuit with fewer and smaller resistors, and a desirably low speed-power product.

Claim 3

The combination as set forth in claim 1, wherein said circuit means includes: means for connecting the base terminal of a first one of said transistors to a reference voltage to provide for essentially constant current through the collector of said first transistor when voltage is applied between its collector and emitter terminals; and means for connecting others of said transistors in a plurality of differential pairs between said first transistor collector and a voltage source, wherein each differential pair has commonly connected emitter terminals, a first differential pair has each of its collector terminals connected to one of said resistors and thence to the voltage source, a second differential pair has its emitter terminals connected to the collector of said first transistor, the remaining ones of said differential pairs are connected between said first and second differential pairs, to provide a selected current path between said voltage source and said first transistor, said current path being determined by the states of complementary pairs of input signals applied to the base terminals of each of said differential pairs, and complementary output signals are obtained at the collector terminals of said first differential pair, said output signals being determined by the states of said input signals and by the interconnected configuration of said differential pairs, to derive a selected logical function of said input signals.

Claim 4

The combination as set forth in claim 2, wherein: said input signals represent one-bit quantities to be added together; and said output signals represent one bit of the arithmetic sum of said input quantities.

Claim 5

A monolithic integrated multiplier circuit comprising: a plurality of NPN transistor devices; and a plurality of resistance devices; said transistor devices and resistance devices being interconnected in current mode logic to form a multiplier circuit having a low speed-power product and being capable of performing parallel multiplication of two multi-digit numerical input quantities, to produce a multi-digit numerical output quantity, and said transistor and resistance devices being formed on a single substrate by a triple diffusion process providing for as low as two-micron feature widths and spacings, for high packing density and a corresponding low defect rate and low production cost, and wherein said resistance devices are formed as unpinched n-type diffusion regions in said substrate, to maintain the high density, low defect rate and low production cost.

Claim 6

A monolithic integrated multiplier circuit comprising: a plurality of NPN transistor devices; and a plurality of resistance devices; said transistor devices and resistance devices being interconnected in current mode logic to form a multiplier circuit having a low speed-power product and being capable of performing parallel multiplication of two multi-digit numerical input quantities, to produce a multi-digit numerical output quantity, and said transistor and resistance devices being formed on a single substrate by a triple diffusion process providing for as low as two-micron feature widths and spacings, for high packing density and a corresponding low defect rate and low production cost, and wherein said resistance devices are formed as unpinched n-type diffusion regions in said substrate, to maintain the high density, low defect rate and low production cost.

Claim 7

A multiplier circuit as set forth in claim 4, wherein: said transistor devices are for the most part connected to provide an arrangement of interconnected logic gates and constant current means, said logic gates including means for steering the constant current through said logic gates in accordance with the states of input signals supplied to said logic gates, thereby to provide output signals derived from said input signals by said arrangement of logic gates.

Claim 8

A multiplier circuit as set forth in claim 5, wherein: said logic gates comprise complementary pairs of said transistors, each of said pairs having its emitter terminals coupled together and having complementary pairs of input signals applied to its respective base terminals, whereby the current supplied by said constant current means is steered through one or the other of the collector circuits of said pair of transistors in accordance with the states of said complementary input signals.

Claim 9

A multiplier circuit as set forth in claim 6, wherein: said constant current means include a plurality of said transistors, each having one of said resistance devices in its emitter circuit and each having its base terminal connected to a fixed reference voltage; and remaining ones of said resistance devices are connected between a voltage source and collector terminals of some of said pairs of transistors, to provide complementary output voltage levels at the collector terminals of at least one of said pairs of transistors, as determined by which one of said pair is in a conductive state.

Claim 10

A multiplier as set forth in claim 4, wherein: each of said transistors has an N type collector region diffused to a depth of approximately 3.5 microns, a P type base region diffused to a depth of approximately 1.2 microns into said collector region, and an N+ type emitter region diffused to a depth of approximately 0.9 micron into said base region.