Current mode multiple-generating register

Claim 2

An improved current mode muliple-generating register for generating multiples of a first binary number which is input thereto, said register being provided with non-functional test (NFT) capabilities, said register comprising: a control circuit comprising a first portion responsive to a 3-bit control signal Y1 Y2 Y4 and a second portion responsive to a first control signal NFTR and to a second control signal NFTS; a clock circuit responsive to a clock signal $ and to a clock-enable signal ¢S; a plurality of data stages, each of which is responsive to a respective bit of said first binary number, each of said data stages further comprising a data selector circuit responsive to said respective bit of said first binary number and further responsive to said control circuit, a master/slave register, said master/slave register being responsive to said clock circuit and further responsive to said data selector circuit, and an output buffer circuit responsive to said master/slave register, whereby said plurality of data stages generate a second binary number which is a multiple of said first binary number in response to said 3-bit control signal.

Claim 3

The improved current mode multiple-generating register recited in claim 1 and further comprising means or providing an NFT-IN signal to the data selector circuit of the first of said plurality of data stages: means for connecting the output of the master/slave register of the last of said plurality of data stages to an additional output buffer circuit for providing an NFT-OUT signal; and means for connecting the outputs of all of said master/slave registers except for said last master/slave register with the data selector circuit of the immediately succeeding data stage, said connections being such that the NFT-IN signal which is input to said first data selector circuit is inverted in each successive data stage.

Claim 4

The improved current mode mulitple-generating register recited in claim 2, wherein each of said data selector circuits further comprises: a current source; a first pair of single input upper level gates responsive to the respective bit of said first binary number for providing a differential output signal depending upon the state of said respective bit, said first pair of single input upper level gates being connected to a first pair of current switching means, said first pair of current switching means being responsive to said 3-bit and NFTS control signals for enabling said first pair of single input upper level gates; and a second pair of single input upper level gates, said second pair of single input upper level gates being responsive to the next higher order input bit, and providing a differential output signal depending upon the state of said next higher order input bit, said second pair of single input upper level gates being connected to a second pair of current switching means, said second pair of current switching means being responsive to said 3-bit NFTR control signals or enabling said second pair of single input upper level gates.

Claim 5

The improved current mode multiple-generating register recited in claim 3 and further comprising a fifth single input upper level gate in first data selector circuit responsive to said NFT-IN signal for providing a differential output signal dependent on the state of said NFT-IN signal; a differential upper level gate in each of said data stages with the exception of said first data stage, said differential upper level gate being responsive to the output of said master/slave register of the preceding data stage and generating a differential output; fifth current switching means responsive to said NFTS signal for enabling said differential upper level gate; sixth current switching means responsive to said NFTS signal for enabling said fifth single input upper level gate; first means in said first data stage for connecting the output of said fifth signal input upper level gate to the outputs of said first and second pairs of single input upper level gates of said data selector circuit; second means in each of the remaining ones of said data stages for connecting the outputs of said first and second pairs of single input upper level gates to the outputs of said differential upper level gates; and seventh current switching means in each of said data selector circuits, said seventh current switching means being responsive to said NFTR signal for generating a logical "O" signal at the output of each of said data selector circuits.

Claim 6

The improved current mode multiple-generating register recited in claim 2, wherein each of said master/slave registers comprises: first, second, third, and fourth differential upper level gates, and first and second differential lower level gates, said first differential lower level gate having its inverting output connected to said first differential upper level gate and its non-inverting output connected to said second differential upper level gate, said second differential lower level gate having its inverting output connected to said third differential upper level gate and its non-inverting output connected to said fourth differential upper level gate; and means for connecting the outputs of said data selector circuit to the inputs of said first differential upper level gate, said outputs of said first differential upper level gate being connected to the inputs of said second differential upper level gate, the output of said second differential upper level gate being connected both to the input thereto and to the input of said third differential upper level gate, the output of said third differential upper level gate being connected to the input of said fourth differential upper level gate, and the output of said fourth differential upper level gate being connected both to the input thereto and to the input of said output buffer circuit.

Claim 7

The improved current mode multiple-generating register recited in claim 1, wherein said control circuit further comprises: a decoding section responsive to said NFTR and said NFTS signals for providing a reset signal, a non-functional test signal, and one of a plurality of mode command signals to each of said data selector circuits, and wherein said clock circuit is responsive to said NFTR signal, said ¢$ signal, and said $ signal for providing a signal S·QM¢$ to each of said master/slave registers.