Asynchronous binary multiplier using non-threshold logic

Claim 1

A multiplier using a sequential-add algorithm to multiply together two binary numbers, said multiplier comprising: a. a first set of signal lines extending in one direction for carrying signals representing the bits of a first number; b. a second set of signal lines extending across said first set for carrying signals representing the bits of a second number, said first and second set of signal lines intersecting to form a matrix, with a single pair of intersecting signal lines forming a single matrix position; and c. logic circuit means for generating the appropriate cross product for each one of said matrix positions and adding that cross product to the appropriately weighted cross products generated at other ones of said matrix positions; the circuitry at each one of said matrix positions comprising 1. means including not more than six input lines for receiving from the circuitry at other matrix positions of said multiplier complementary binary signals representing sum or carry inputs; 2. means including not more than two lines for receiving external binary signals representing one bit of each of the numbers to be multiplied together; 3. a first plurality of logic circuits for forming the appropriate complementary binary signals representing cross products between the external signals; 4. a second plurality of non-threshold logic gates connected to receive the complementary binary signals from said first plurality of logic circuits and connected with said input lines to form not more than eight AND gates; 5. a third plurality of non-threshold logic gates connected to the outputs of said AND gates to form four OR gates; and 6. means including not more than four output lines connected to the outputs of said OR gates for transmitting to succeeding stages of said multiplier complementary binary signals representing sum and carry outputs respectively.