← Back to Patent Explorer
US3752971A Expired / Lapsed US ⏱️ 0.0 years remaining

Expandable sum of cross product multiplier/adder module

Assignee: Raytheon Co
•
Filing: 1971-10-18
•
Granted: 1973-08-14
•
Expires: 1991-10-18
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A high speed digital multiplier which includes a plurality of functionally and structurally identical multiplier modules. Each multiplier module is adapted to perform an N X N bit multiplication. In addition, each module accepts product bits and carry bits from other multiplier modules and adds them to the N X N bit product according to the appropriate bit weights. Several modules are interconnected for M X M bit multiplications where M is greater than N. The modules contain all the circuitry necessary for performing the multiplication.

Inventors

  • 👤 D Calhoun
  • 👤 R Ziff

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 00:01
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5306; G06F7/5312; G06F7/5324

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 159 words
A modular digital circuit for forming a final product of at least 4N bits from first and second binary words each having at least 2N bits, said circuit comprising a plurality of substantially identical interconnected multiplier/adder circuit modules including a first order module and a plurality of higher order modules, wherein: the output from each of said modules provides 2N product bits and two carry bits, the 2N product bits from said first order module forming the lowest weight 2N bits of said final product; said first order module has a first set of inputs coupled to receive the lowest weight N bits from each of said first and second binary words respectively; and said first order module has a second set of inputs coupled to receive two additional groups of N bits, said groups forming respectively the N lowest weight product bits output from each of two second order modules included within said plurality of higher order modules.
Claim 2
Dependent Claim 159 words
A modular digital circuit for forming a final product of at least 4N bits from first and second binary words each having at least 2N bits, said circuit comprising a plurality of substantially identical interconnected multiplier/adder circuit modules including a first order module and a plurality of higher order modules, wherein: the output from each of said modules provides 2N product bits and two carry bits, the 2N product bits from said first order module forming the lowest weight 2N bits of said final product; said first order module has a first set of inputs coupled to receive the lowest weight N bits from each of said first and second binary words respectively; and said first order module has a second set of inputs coupled to receive two additional groups of N bits, said groups forming respectively the N lowest weight product bits output from each of two second order modules included within said plurality of higher order modules.
Claim 3
Dependent Claim 36 words
The modular digital circuit of claim 1 in which N is an integer equal to or greater than four and the maximum word length of said first and second binary words is a multiple of N.
Claim 4
Dependent Claim 34 words
The circuit of claim 1 wherein a particular one of said two second order modules has a third set of inputs coupled to receive said two carry bits output from said first order module.
Claim 5
Dependent Claim 61 words
An expandable sum of cross products multiplier/adder module comprising: means for forming the 8 bit cross product from two 4 bit inputs; means for adding to the most significant 4 bits of said cross product two additional 4 bit inputs; and means for adding to the fifth and sixth most significant bits of said cross product a 2 bit carry input.
Claim 6
Dependent Claim 61 words
An expandable sum of cross products multiplier/adder module comprising: means for forming the 8 bit cross product from two 4 bit inputs; means for adding to the most significant 4 bits of said cross product two additional 4 bit inputs; and means for adding to the fifth and sixth most significant bits of said cross product a 2 bit carry input.
Claim 7
Dependent Claim 15 words
The module of claim 1, further comprising means for outputting a 2 bit carry output.

References Cited (Backward Citations)

US3407290A Cited
US3670956A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-08-13 1977-02-12 1977-08-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-08-13 1981-02-12 1981-08-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-08-13 1985-02-12 1985-08-14 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag