EP0606001A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Process of fabrication of bipolar and field effect transistors
Assignee: NEC Corp
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Filing: 1993-12-22
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Granted: —
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Expires: 2013-12-22
Abstract
Abstract In a process of fabricating a miniature transistor, an undercut is formed beneath a periphery of a doped polysilicon layer (16) over an active area, and a piece of polysilicon (19a) is left in the undercut by etching a polysilicon film covering the entire surface without oxidation for diffusing a dopant impurity from the doped polysilicon (16) through the piece of polysilicon (19a) into the active area (24), thereby preventing the active area from stress.
Inventors
- 👤 Chihiro Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 08:49
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/061; H10D10/051; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D62/80; H10D62/83; H10D62/834; H10D64/00; H10D64/60; H10D64/62; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
331 words
A process of fabricating a transistor on a semiconductor substrate (11/12/13; 31/32), comprising the steps of: a) forming a multi-layered structure of a first insulating layer (15; 34) on an active area defined in a major surface of said semiconductor substrate, a first conductive layer (16; 35) of a semiconductor substance doped with a first dopant impurity and formed on said first insulating layer and a second insulating layer (17; 36) formed on said first conductive layer; b) partially removing said second insulating layer and said first conductive layer for forming a hole (18; 37) exposing a first part of said first insulating layer in a central sub-area of said active area; c) etching said first part of said first insulating layer and a second part of said first insulating layer contiguous to said first part and overlain by a periphery of said first conductive layer for forming an undercut (15a) beneath said periphery of said first conductive layer; d) depositing a second conductive layer (19) of said semiconductor substance over the entire surface, said undercut being filled with said semiconductor substance; e) removing said second conductive layer except for a piece (19a; 38a) of said semiconductor substance in said undercut; and f) completing said transistor by forming a plurality of impurity regions (20/23/24; 41a/41b; 50/51), at least one electrode (22; 42;2) and an insulating side wall (21; 39) covering a side surface of said first conductive layer exposed to said hole, a side surface of said second insulating layer exposed to said hole and a side surface of said piece of said semiconductor substance exposed to said hole, at least one (19a; 41a/41b; 50/51) of said plurality of impurity regions being formed through a diffusion of said first dopant impurity from said first conductive layer through said piece of said semiconductor substance into a peripheral sub-area of said active area, characterized in that an etching technique selectively removes said second conductive layer without any oxidation stage in said step e).
Claim 2
Dependent Claim
162 words
The process as set forth in claim 1, in which said step f) comprises the sub-steps of f-1) introducing a second dopant impurity through said hole into said semiconductor substrate for forming another of said plurality of impurity regions serving as a base region (20), f-2) forming said insulating side wall (21) for defining a secondary hole (18), f-3) forming a third conductive layer (22) doped with a third dopant impurity held in contact with a part of said central sub-area exposed to said secondary hole, said third conductive layer corresponding to said at least one electrode serving as an emitter electrode, and f-4) applying heat for diffusing said first dopant impurity and said third dopant impurity into said peripheral sub-area and said part of said central sub-area, thereby forming said one (24) of said plurality of impurity regions serving as a base contact region and contiguous to said base region (20) and an emitter region (23) nested with said base region.
Claim 3
Dependent Claim
166 words
The process of fabricating a transistor as set forth in claim 1, in which said hole (37) separates said first conductive layer (35) into two portions (35a/ 35b) electrically isolated from each other, and in which said step f) comprises the sub-steps of f-1) forming said insulating side wall (39) for defining a secondary hole (37a), f-2) applying heat for thermally oxidizing a part of said central sub-area exposed to said secondary hole and for diffusing said first dopant impurity into said peripheral sub-area, said part of said central sub-area thermally oxidized serving as a gate insulating film (40), said first dopant impurity diffused into said peripheral sub-area forming said one of said plurality of impurity regions serving as a drain region (41a) and another of said plurality of impurity regions serving as a source region (41b), and f-3) forming a third conductive layer held in contact with said gate insulating film and corresponding to said at least one electrode serving as a gate electrode (42).
Claim 4
Dependent Claim
155 words
The process as set forth in claim 1, in which said hole (37) separates said first conductive layer (35) into two portions (35a/35b) electrically isolated from each other, and in which said step f) comprises the sub-steps of f-1) forming said insulating side wall(39) for defining a secondary hole (37a), f-2) applying heat for diffusing said first dopant impurity into said peripheral sub-area for forming said one of said plurality of impurity regions serving as an emitter region (50) and another of said plurality of impurity regions serving as a collector region (51), f-3) forming a third conductive layer (52) doped with a second dopant impurity and held in contact with a part of the central sub-area, and f-4) rapidly heating said third conductive layer for diffusing said second dopant impurity into said part of said central sub-area, thereby forming a base contact region (53) serving as yet another of said plurality of impurity regions.
Claim 5
Dependent Claim
107 words
A process of fabricating a semiconductor device, wherein an undercut is formed beneath a periphery of a doped conductive layer (16) over an active area (24), and a piece of a second semiconductor substance (19a) is disposed in the undercut for diffusing a dopant impurity from the first semiconductor layer (16) through the second semiconductor substance (19a) into the active area (24), characterised by depositing said second conductor substance as a layer (19) over a surface to which the undercut is open, so as to fill the undercut with the second semiconductor substance (19a), and removing said layer (19) except in the undercut by etching without oxidation.
References Cited (Backward Citations)
No citation records indexed.
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