US4965217A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a lateral transistor
Assignee: International Business Machines Corp
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Filing: 1989-04-13
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Granted: 1990-10-23
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Expires: 2009-04-13
Abstract
Abstract A method of fabricating a lateral transistor is provided, including the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of the device region to define a first transistor region; filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of with first transistor region; removing portions of the insulating material so as to define a pair of trenches generally bonding opposite sides of the first transistor region; filling the pair of trenches with doped conductive material of opposite conductivity type to the first transistor region; and annealing the semiconductor body whereby to form second and third transistor regions of opposite conductivity type to the first transistor region in the opposing sides of the first transistor region.
Inventors
- 👤 Brian H. Desilets
- 👤 Chang-Ming Hsieh
- 👤 Louis L. Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:02
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/061; H10D10/60; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
217 words
A method of fabricating a lateral transistor comprising the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of said device region to define a first transistor region; filling the patterned portion of said device region surrounding said first transistor region with an insulating material to a height generally equal to the surface of said first transistor region; forming a layer of conductive material over the surface of said device region; anisotropically etching said layer of conductive material and said insulating material so as to define a pair of trenches generally bounding opposite sides of said first transistor region and so as to form exposed edges of said layer of conductive material adjacent each of said trenches; filling said pair of trenches with doped conductive material of opposite conductivity type to said first transistor region such that said doped conductive material extends into contact with the exposed edges of said layer of conductive material; and heating said semiconductor body whereby to form second and third transistor regions of opposite conductivity type to said first transistor region in the opposing sides of said first transistor region and whereby to form electrical connections between said doped conductive material and the exposed edges of said layer of conductive material.
Claim 2
Independent Claim
217 words
A method of fabricating a lateral transistor comprising the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of said device region to define a first transistor region; filling the patterned portion of said device region surrounding said first transistor region with an insulating material to a height generally equal to the surface of said first transistor region; forming a layer of conductive material over the surface of said device region; anisotropically etching said layer of conductive material and said insulating material so as to define a pair of trenches generally bounding opposite sides of said first transistor region and so as to form exposed edges of said layer of conductive material adjacent each of said trenches; filling said pair of trenches with doped conductive material of opposite conductivity type to said first transistor region such that said doped conductive material extends into contact with the exposed edges of said layer of conductive material; and heating said semiconductor body whereby to form second and third transistor regions of opposite conductivity type to said first transistor region in the opposing sides of said first transistor region and whereby to form electrical connections between said doped conductive material and the exposed edges of said layer of conductive material.
Claim 3
Dependent Claim
55 words
A method in accordance with claim 1 wherein said step of filling the patterned portions of said body with an insulating material comprises the steps of: forming a thin layer of thermal oxide on the patterned surfaces of said body; and depositing by chemical vapor deposition an oxide over said thin layer of thermal oxide.
Claim 4
Dependent Claim
83 words
A method in accordance with claim 1 wherein said step of filling said pair of trenches with doped conductive material includes the steps of: forming a layer of said doped conductive material generally conformally over the surface of the device including the exposed edges of said layer of conductive material and into said trenches; and anisotropically etching said layer of doped conductive material to leave portions filling said trenches and extending into contact with the exposed edges of said layer of conductive material.
Claim 5
Dependent Claim
56 words
A method in accordance with claim 3 and further including the steps of: forming a layer of insulating material over said layer of conductive material before said step of forming said layer of doped conductive material; and removing the portions of said layer of insulating material overlying said first transistor region and said pair of trenches.
Claim 6
Dependent Claim
37 words
A method in accordance with claim 4 and further including the step of doping said first transistor region exposed by removing portion of said layers of conductive and insulating materials with impurities of said first conductivity type.
Claim 7
Dependent Claim
63 words
A method in accordance with claim 1 and further including the steps of: forming a protective layer of nitride over the exposed surfaces of said first transistor region before said step of filling said pair of trenches; and forming a protective layer of oxide over the exposed top surface of said first transistor region before said step of filling said pair of trenches.
References Cited (Backward Citations)
US4333227A
Cited
US4378630A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |