Vertical bipolar transistor with recessed epitaxially grown intrinsic base region

Claim 1

A method of manufacturing a vertical bipolar transistor comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; etching the surface of said first region to form a recess in said first region; forming by epitaxial growth a layer of semiconductor materials of a second conductivity type on said etched surface of said first region said layer comprising a layer of single crystal structure on at least said recess, and heating to form an intrinsic region of said first conductivity type in the surface of said intrinsic base region while substantially simultaneously forming a second region of said first conductivity type in the surface of said intrinsic base region.

Claim 2

A method of manufacturing a vertical bipolar transistor comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; etching the surface of said first region to form a recess in said first region; forming by epitaxial growth a layer of semiconductor materials of a second conductivity type on said etched surface of said first region said layer comprising a layer of single crystal structure on at least said recess, and heating to form an intrinsic region of said first conductivity type in the surface of said intrinsic base region while substantially simultaneously forming a second region of said first conductivity type in the surface of said intrinsic base region.

Claim 11

A method of manufacturing a vertical bipolar transistor comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of said first region, said extrinsic base region generally bounding a portion of said first region; forming by ion implantation a linking region of said second conductivity type in the surface of said bounded portion of said first region so as to electrically link generally opposing edges of said extrinsic base region through said linking region; forming an insulating spacer over the junction between said extrinsic base region and said linking region so as to generally bound a portion of said linking region within said portion of said first region; etching the surface of said bounded portion of said linking region a short distance into said linking region; forming by epitaxial growth a first layer of semiconductor material of said second conductivity type on said etched surface of said bounded portion of said linking region, said first layer comprising a layer of single crystal structure on at least said recess, and heating said semiconductor substrate to form an intrinsic base region at least partially within said first layer and to form an electrical connection between said intrinsic and extrinsic base regions through said linking region while substantially simultaneously forming a second region of said first conductivity type in the surface of said intrinsic base region.

Claim 12

A method of manufacturing a vertical bipolar transistor comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of said first region, said extrinsic base region generally bounding a portion of said first region; forming by ion implantation a linking region of said second conductivity type in the surface of said bounded portion of said first region so as to electrically link generally opposing edges of said extrinsic base region through said linking region; forming an insulating spacer over the junction between said extrinsic base region and said linking region so as to generally bound a portion of said linking region within said portion of said first region; etching the surface of said bounded portion of said linking region a short distance into said linking region; forming by epitaxial growth a first layer of semiconductor material of said second conductivity type on said etched surface of said bounded portion of said linking region, said first layer comprising a layer of single crystal structure on at least said recess, and heating said semiconductor substrate to form an intrinsic base region at least partially within said first layer and to form an electrical connection between said intrinsic and extrinsic base regions through said linking region while substantially simultaneously forming a second region of said first conductivity type in the surface of said intrinsic base region.

Claim 19

A method of manufacturing a vertical bipolar transistor comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of said first region, said extrinsic base region generally bounding a portion of said first region; forming by ion implantation a linking region of said second conductivity type in the surface of said bounded portion of said first region, forming an insulating spacer over the junction between said extrinsic base region and said linking region so as to generally bound a portion of said linking region with said bounded portion of said first region, etching the surface of said linking region to form a recess in said linking region; forming by epitaxial growth a layer of semiconductor material of said second conductivity type on said etched surface of said linking region, said steps of etching the surface of said first region and forming by epitaxial growth said layer of semiconductor material being performed in said bounded portion of said linking region; heating said semiconductor substrate to form an intrinsic base region of said second conductivity type at least partially within said layer of semiconductor material, said intrinsic base region formed within the bounded portion of said first region and linked to said extrinsic base region by said linking region, and forming a second region of said first conductivity type in the surface of said intrinsic base region.

Claim 20

A method of manufacturing a vertical bipolar transistor comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of said first region, said extrinsic base region generally bounding a portion of said first region; forming by ion implantation a linking region of said second conductivity type in the surface of said bounded portion of said first region, forming an insulating spacer over the junction between said extrinsic base region and said linking region so as to generally bound a portion of said linking region with said bounded portion of said first region, etching the surface of said linking region to form a recess in said linking region; forming by epitaxial growth a layer of semiconductor material of said second conductivity type on said etched surface of said linking region, said steps of etching the surface of said first region and forming by epitaxial growth said layer of semiconductor material being performed in said bounded portion of said linking region; heating said semiconductor substrate to form an intrinsic base region of said second conductivity type at least partially within said layer of semiconductor material, said intrinsic base region formed within the bounded portion of said first region and linked to said extrinsic base region by said linking region, and forming a second region of said first conductivity type in the surface of said intrinsic base region.

Claim 21

A method of manufacturing a vertical bipolar transistor comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of said first region, said extrinsic base region generally bounding a portion of said first region, wherein said step of forming said extrinsic base region comprises the steps of: a) forming an extrinsic base contact of a conductive material containing dopant of said second conductivity type over said first region; and b) heating said substrate to drive said dopant from said extrinsic base region into said first region; forming by ion implantation a linking region of said second conductivity type in the surface of said bounded portion of said first region so as to electrically link generally opposing edges of said extrinsic base region through said linking region; forming an insulating spacer over the junction between said extrinsic base region and said linking region so as to generally bound a portion of said linking region within said portion of said first region, wherein said step of forming an insulating spacer comprises the steps of: a) forming a layer of insulating material generally conformally over said extrinsic base contact and said bounded portion of said first region; and b) reactive ion etching said layer of insulating material so as to form said insulating spacer; etching the surface of said bounded portion of said linking region a short distance into said linking region, wherein said step of etching the surface of said bounded portion of said linking region comprises the steps of: a) continuing said reactive ion etching step into the surface of said bounded portion of said linking region; b) oxidizing the surface of said bounded portion of said linking region to form a thin layer of oxide; and c) removing said thin layer of oxide, such that any defects in the surface of said bounded portion of said linking region caused by said reactive ion etching step are substantially removed by said oxidizing and removing steps; removing by epitaxial growth a first layer of semiconductor material of said second conductivity type on said etched surface of said bounded portion of said linking region; heating said semiconductor substrate to form an intrinsic base region at least partially within said first layer and to form an electrical connection between said intrinsic and extrinsic base regions through said linking regions; and forming a second region of said first conductivity type in the surface of said intrinsic base region.

Claim 22

A method of manufacturing a vertical bipolar transistor comprising the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of said first region, said extrinsic base region generally bounding a portion of said first region, wherein said step of forming said extrinsic base region comprises the steps of: a) forming an extrinsic base contact of a conductive material containing dopant of said second conductivity type over said first region; and b) heating said substrate to drive said dopant from said extrinsic base region into said first region; forming by ion implantation a linking region of said second conductivity type in the surface of said bounded portion of said first region so as to electrically link generally opposing edges of said extrinsic base region through said linking region; forming an insulating spacer over the junction between said extrinsic base region and said linking region so as to generally bound a portion of said linking region within said portion of said first region, wherein said step of forming an insulating spacer comprises the steps of: a) forming a layer of insulating material generally conformally over said extrinsic base contact and said bounded portion of said first region; and b) reactive ion etching said layer of insulating material so as to form said insulating spacer; etching the surface of said bounded portion of said linking region a short distance into said linking region, wherein said step of etching the surface of said bounded portion of said linking region comprises the steps of: a) continuing said reactive ion etching step into the surface of said bounded portion of said linking region; b) oxidizing the surface of said bounded portion of said linking region to form a thin layer of oxide; and c) removing said thin layer of oxide, such that any defects in the surface of said bounded portion of said linking region caused by said reactive ion etching step are substantially removed by said oxidizing and removing steps; removing by epitaxial growth a first layer of semiconductor material of said second conductivity type on said etched surface of said bounded portion of said linking region; heating said semiconductor substrate to form an intrinsic base region at least partially within said first layer and to form an electrical connection between said intrinsic and extrinsic base regions through said linking regions; and forming a second region of said first conductivity type in the surface of said intrinsic base region.