Method for forming a thick base oxide in a BiCMOS process

Claim 1

A method for fabricating an integrated circuit, comprising: `forming isolation structures at a semiconductor surface of a body, said isolation structures defining a bipolar region and a first MOS region, both of a first conductivity type, and a second MOS region of a second conductivity type; forming an insulating layer abutting said bipolar region, said first MOS region, and said second MOS region; forming a first conductive layer abutting said insulating layer; introducing base dopant of said second conductivity type into said bipolar region after formation of said insulating layer; removing said first conductive layer from said bipolar region; forming a dielectric layer thereover, said dielectric layer overlying said first conductive layer at said MOS regions and overlying said bipolar region; removing a selected portion of said dielectric layer to expose a portion of said bipolar region, and to expose said first conductive layer in said MOS regions; forming a second conductive layer thereover, said second conductive layer in contact with said exposed portion of said bipolar region and in contact with said first conductive layer in said MOS regions; forming an emitter region at the location at which said second conductive layer is in contact with said bipolar region; and removing selected portions of said second conductive layer in said bipolar region to define an emitter electrode, and selected portions of said first and second conductive layers in said MOS regions to define gate electrodes.

Claim 2

A method for fabricating an integrated circuit, comprising: `forming isolation structures at a semiconductor surface of a body, said isolation structures defining a bipolar region and a first MOS region, both of a first conductivity type, and a second MOS region of a second conductivity type; forming an insulating layer abutting said bipolar region, said first MOS region, and said second MOS region; forming a first conductive layer abutting said insulating layer; introducing base dopant of said second conductivity type into said bipolar region after formation of said insulating layer; removing said first conductive layer from said bipolar region; forming a dielectric layer thereover, said dielectric layer overlying said first conductive layer at said MOS regions and overlying said bipolar region; removing a selected portion of said dielectric layer to expose a portion of said bipolar region, and to expose said first conductive layer in said MOS regions; forming a second conductive layer thereover, said second conductive layer in contact with said exposed portion of said bipolar region and in contact with said first conductive layer in said MOS regions; forming an emitter region at the location at which said second conductive layer is in contact with said bipolar region; and removing selected portions of said second conductive layer in said bipolar region to define an emitter electrode, and selected portions of said first and second conductive layers in said MOS regions to define gate electrodes.

Claim 15

A method of fabricating an MOS device and a transistor on a semiconductor substrate, said method comprising: forming a gate dielectric layer abutting said substrate; depositing a first conductive layer abutting said gate dielectric layer; patterning said first conductive layer to expose a portion of said gate dielectric layer; introducing a first conductivity type dopant into selective portions of said substrate through said exposed portion of said gate dielectric layer; forming a thick dielectric abutting said patterned first conductive layer and said exposed portion of said gate dielectric layer; patterning said thick dielectric and said gate dielectric layer to expose a portion of said substrate and portions of said patterned first conductive layer; forming a second conductive layer abutting said exposed portion of said substrate, said patterned thick dielectric, and said exposed portions of said patterned first conductive layer, and patterning said second conductive layer to transistor electrode and patterning selected portions of said first and said second conductive layers in the MOS region to form a gate electrode.

Claim 16

A method of fabricating an MOS device and a transistor on a semiconductor substrate, said method comprising: forming a gate dielectric layer abutting said substrate; depositing a first conductive layer abutting said gate dielectric layer; patterning said first conductive layer to expose a portion of said gate dielectric layer; introducing a first conductivity type dopant into selective portions of said substrate through said exposed portion of said gate dielectric layer; forming a thick dielectric abutting said patterned first conductive layer and said exposed portion of said gate dielectric layer; patterning said thick dielectric and said gate dielectric layer to expose a portion of said substrate and portions of said patterned first conductive layer; forming a second conductive layer abutting said exposed portion of said substrate, said patterned thick dielectric, and said exposed portions of said patterned first conductive layer, and patterning said second conductive layer to transistor electrode and patterning selected portions of said first and said second conductive layers in the MOS region to form a gate electrode.