US4931407A
Expired / Lapsed
US
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Method for manufacturing integrated bipolar and MOS transistors
Assignee: Toshiba Corp
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Filing: 1988-06-24
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Granted: 1990-06-05
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Expires: 2008-06-24
Abstract
Abstract A method for manufacturing MOS and bipolar transistors is proposed which includes MOS and bipolar transistors. The method comprises implanting impurity ions in a channel formation region with a dummy gate insulating film interposed and, subsequent to forming a gate oxide film on the surface of the resultant structure, impurity ions are implanted into an internal base region of the bipolar transistor.
Inventors
- 👤 Takeo Maeda
- 👤 Koji Makita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:39
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
55 words
A method for manufacturing a semiconductor device comprising the steps of: (a) implanting impurity ions into a channel formation region for forming a MOS transistor with a dummy gate insulating film interposed; and (b) implanting impurity ions into an internal base formation region for forming a bipolar transistor subsequent to forming a gate insulating film.
Claim 2
Independent Claim
55 words
A method for manufacturing a semiconductor device comprising the steps of: (a) implanting impurity ions into a channel formation region for forming a MOS transistor with a dummy gate insulating film interposed; and (b) implanting impurity ions into an internal base formation region for forming a bipolar transistor subsequent to forming a gate insulating film.
Claim 3
Dependent Claim
144 words
The method according to claim 1, in which, an emitter electrode of said bipolar transistor is formed by depositing a first poly-Si layer 500 to 20000 A thick on said gate insulating film during said step (b); opening an emitter contact hole by etching said poly-Si layer and said gate insulating film to form said emitter contact hole; and subsequent to forming said emitter contact hole a second poly-Si layer 100 to 1000 A thick is deposited on a surface of the resultant semiconductor substrate and As ions are implanted at an acceleration voltage of 40 to 100 KeV and dose of 5×10 15 cm -2 to 2×10 16 cm -2 into the surface portion of the semiconductor substrate with said poly-Si layer interposed to provide an emitter electrode, whereby said gate insulating film is protected and the resistance of said emitter is lowered.
Claim 4
Dependent Claim
39 words
The method according to claim 2 in which subsequent to forming said emitter electrode a heat treatment is conducted on the resultant semiconductor structure for 10 to 60 seconds at 950 to 1100° C. to reduce the emitter resistance.
Claim 5
Dependent Claim
18 words
The method according to claim 3, wherein said heat treatment is performed after an insulating interlayer is re-flowed.
Claim 6
Dependent Claim
39 words
The method according to claim 2, in which subsequent to forming said emitter electrode a heat treatment is conducted on the resultant semiconductor structure for 10 to 60 seconds at 950 to 1100° C. to reduce the emitter resistance.
Claim 7
Dependent Claim
18 words
The method according to claim 5, wherein said heat treatment is performed after an insulating interlayer is re-flowed.
Claim 8
Independent Claim
194 words
A method for manufacturing a semiconductor device comprising the steps of: (a) implanting impurity ions into a MOS transistor formation region in a surface portion of a semiconductor substrate to allow control of a threshold voltage level; (b) forming a gate electrode over said MOS transistor formation area; (c) forming source and drain regions of the MOS transistor by implanting impurity ions using said electrode as a mask; (d) forming an external base region by implanting impurity ions in a bipolar transistor formation area; (e) forming an internal base region, which contacts said external base region, by implanting impurity ions into said bipolar transistor formation area; (f) depositing an insulating interlayer on an entire surface of a resultant semiconductor structure; (g) forming in said insulating interlayer an opening which reaches a surface of said internal base region; (h) subsequent to depositing a poly-Si layer on an entire surface of the resultant semiconductor structure, leaving a portion of said poly-Si layer at an area near said opening; and (i) forming an emitter region and an emitter electrode of said bipolar transistor by implanting impurity ions into said internal base region with said poly-Si layer interposed.
Claim 9
Independent Claim
194 words
A method for manufacturing a semiconductor device comprising the steps of: (a) implanting impurity ions into a MOS transistor formation region in a surface portion of a semiconductor substrate to allow control of a threshold voltage level; (b) forming a gate electrode over said MOS transistor formation area; (c) forming source and drain regions of the MOS transistor by implanting impurity ions using said electrode as a mask; (d) forming an external base region by implanting impurity ions in a bipolar transistor formation area; (e) forming an internal base region, which contacts said external base region, by implanting impurity ions into said bipolar transistor formation area; (f) depositing an insulating interlayer on an entire surface of a resultant semiconductor structure; (g) forming in said insulating interlayer an opening which reaches a surface of said internal base region; (h) subsequent to depositing a poly-Si layer on an entire surface of the resultant semiconductor structure, leaving a portion of said poly-Si layer at an area near said opening; and (i) forming an emitter region and an emitter electrode of said bipolar transistor by implanting impurity ions into said internal base region with said poly-Si layer interposed.
Claim 10
Dependent Claim
33 words
The method according to claim 7, in which said poly-Si layer is left at an area near said opening and at another area to form a high resistance element at said another area.
Claim 11
Dependent Claim
37 words
The method according to claim 7, in which said gate electrode is formed of at least one material selected from the group consisting of a poly-Si layer, high melting point metal layer and high melting joint silicide.
Claim 12
Dependent Claim
52 words
The method according to claim 7, in which said emitter region and said emitter electrode are formed by implanting impurity ions into said portion of said poly-Si layer at said opening, at an acceleration of 40 to 100 KeV and dose of 5×10 15 /cm 2 to 2×10 16 /cm 2 ,
Claim 13
Dependent Claim
39 words
The method according to claim 7, in which, subsequent to forming said emitter region and said emitter electrode, a heat treatment is conducted for 5 seconds to one minute at 950° to 1150° C. on the resultant semiconductor structure.
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| 3.5 Years (Year 4) | 1993-06-04 | 1993-12-04 | 1994-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-04 | 1997-12-04 | 1998-06-05 | $3760.00 | Window Closed / Lapsed |
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