EP0224712A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Integrated device comprising bipolar and complementary metal oxide semiconductor transistors
Assignee: Texas Instruments Inc
•
Filing: 1986-10-27
•
Granted: —
•
Expires: 2006-10-27
Abstract
Abstract A method of making an integration of bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts including silicide and interconnects are deposited and patterned.
Inventors
- 👤 Douglas Verret
- 👤 Michael C. Smayling
- 👤 Abnash C. Sachdeva
- 👤 Stephen A. Keller
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 10:44
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10P; H10P36/00; H10P36/03; H10W10/10; H10W10/17; H10W15/00; H10W15/01; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
92 words
A method of making a merged bipolar and field effect transistor on a semiconductor substrate of a first conductivity type, comprising; forming a diffused buried DUF collector region of a second conductivity type in said substrate; growing a silicon epitaxial layer of the second conductivity type over said substrate; forming FET and bipolar isolation regions in said epitaxial layer; forming a bipolar transistor over said DUF region within said bipolar isolation region; forming a field effect transistor within said FET isolation region; and depositing and patterning of metal contacts to said transistors.
Claim 2
Independent Claim
92 words
A method of making a merged bipolar and field effect transistor on a semiconductor substrate of a first conductivity type, comprising; forming a diffused buried DUF collector region of a second conductivity type in said substrate; growing a silicon epitaxial layer of the second conductivity type over said substrate; forming FET and bipolar isolation regions in said epitaxial layer; forming a bipolar transistor over said DUF region within said bipolar isolation region; forming a field effect transistor within said FET isolation region; and depositing and patterning of metal contacts to said transistors.
Claim 3
Dependent Claim
19 words
A method according to claim 1, wherein processing steps in forming said bipolar and FET transistors are done concurrently.
Claim 4
Dependent Claim
139 words
A method according to claim 2, wherein said transistor forming steps include: forming a moat region in said FET isolation region; forming an oxide insulated gate over said moat; implanting said moat with a first selected impurity of a conductivity type different than that of said moat to form source and drain regions therefor; implanting the epitaxial layer within said bipolar isolation region with a second selected impurity of a first conductivity type to form a base of a bipolar transistor overlying a collector portion of said buried DUF region; implanting a third selected impurity within said base of a second conductivity type for an emitter region therein; implanting a fourth selected impurity of the second conductivity type in said bipolar isolation region to form a deep collector contact; and heating said transistors to activate and diffuse the implants.
Claim 5
Dependent Claim
35 words
A method according to claim 3, wherein said isolation regions are formed by etching recessed regions into said epitaxial layer and then growing thick oxide regions in said recessed regions extending through said epitaxial layer.
Claim 6
Independent Claim
91 words
A method of making a merged bipolar and complementary field effect transistors on a semiconductor substrate of a first conductivity type, comprising: forming a diffused buried DUF collector region of a second conductivity type in a face of said substrate; growing a silicon epitaxial layer of the second conductivity type over said substrate; forming FET isolation regions and a bipolar isolation region in said epitaxial layer; forming a bipolar transistor over said DUF region within said bipolar isolation region; and forming complementary field effect transistors within said field effect transistor regions.
Claim 7
Independent Claim
91 words
A method of making a merged bipolar and complementary field effect transistors on a semiconductor substrate of a first conductivity type, comprising: forming a diffused buried DUF collector region of a second conductivity type in a face of said substrate; growing a silicon epitaxial layer of the second conductivity type over said substrate; forming FET isolation regions and a bipolar isolation region in said epitaxial layer; forming a bipolar transistor over said DUF region within said bipolar isolation region; and forming complementary field effect transistors within said field effect transistor regions.
Claim 8
Dependent Claim
103 words
A method according to claim 5, wherein said transistor forming steps include: forming moat regions in said FET isolation regions; forming oxide insulated gates over respective moat regions; implanting source/drain regions in each of said moats of a conductivity type opposite to that of the respective moats; implanting a base region in said bipolar isolation region of a conductivity type opposite to that of the underlying DUF region; implanting an emitter within said base of a conductivity type opposite to that of the base; implanting a deep collector contact in said bipolar region; and heating said transistors to activate and diffuse the implants.
Claim 9
Dependent Claim
39 words
A method according to claim 6, wherein said isolation regions are formed by etching recessed regions into said epitaxial layer enclosing respective isolation regions and then growing thick oxide regions in said recessed regions extending through said epitaxial layer.
Claim 10
Dependent Claim
31 words
A method according to claim 6, including forming a channel stop region of a P-type conductivity in a face of said substrate below an N-channel one of said field effect transistors.
Claim 11
Dependent Claim
36 words
A method according to claim 5, wherein the edges of each of said source/drain regions of said field effect transistors are space away from associated adjacent isolation regions so as not to form an interface, therewith.
Claim 12
Dependent Claim
56 words
A method according to claim 6, wherein the source/drain implant of a P-channel one of said field effect transistors, and the base implant of said bipolar transistor base are boron, the implants of said buried collector and the source/drain regions of the N-channel field transistors are arsenic, and that of the collector contact region is phosphorus.
Claim 13
Dependent Claim
18 words
A method according to claim 8, wherein a P-type well region is formed above the channel stop region.
Claim 14
Dependent Claim
13 words
A method according to claim 11, wherein said P-type well implant is boron.
Claim 15
Dependent Claim
65 words
A method according to claim 6, wherein surface contact to said buried collector portion is made by a deep implant having a peak concentration approximately half way into said epitaxial layer and a shallow implant having a peak concentration of implanted atoms at or near a surface of said epitaxial region and then diffusing and activating the implanted impurities and the underlying buried collector portion.
Claim 16
Dependent Claim
24 words
A method according to claim 5, wherein said implanting steps of said P-channel transistor are done concurrently with implanting steps of said bipolar transistors.
Claim 17
Dependent Claim
52 words
A method according to claim 6, including depositing a surface gettering layer over said semiconductor surface prior to said annealing and diffusing and then patterning and etching the gettering layer so as to open up contact areas to the field transistor sources and drains, and the bipolar transistor emitter, base and collector.
Claim 18
Dependent Claim
57 words
A method according to claim 6, including depositing a surface gettering layer over the semiconductor surface after said annealing and diffusing and then patterning and etching the gettering layer so as to open up contact areas to the field effect transistor sources, drains and emitter, base and collector so as to improve device fabrication control and performance.
Claim 19
Dependent Claim
14 words
A method according to claim 14, wherein said surface gettering layer is phospho-silicate glass.
Claim 20
Dependent Claim
48 words
A method according to claim 6, wherein said moat regions are formed by deposition, patterning and developing photoresist to open the moat areas and subsequent etching of underlying oxide to expose the moat areas so that the moat edges are spaced apart from the field oxide isolation regions.
Claim 21
Dependent Claim
16 words
A method according to claim 18, wherein said gettering layer is heated so that it reflows.
Claim 22
Dependent Claim
50 words
A method according to claim 6, including opening transistor contacts to the sources, drains and gates of said field effect transistors and to the emitter, base and collector of the bipolar transistor and forming a layer of silicide over each of said transistor contacts prior to deposition of metal thereon.
Claim 23
Dependent Claim
114 words
A merged bipolar and complementary field effect transistors formed on a semiconductor substrate of a first conductivity type, comprising: a diffused buried DUF region of a second conductivity type formed in a face of said substrate; an epitaxial layer of said second conductivity type formed on a face of said substrate; a plurality of oxide isolation regions formed in said epitaxial layer; a first field effect transistor formed in a first FET one of said oxide isolation regions; a bipolar transistor formed in a bipolar one of said oxide isolation regions above said diffused buried region having an emitter, base, and collector wherein said base has an intrinsic portion and an extrinsic portion of
Claim 24
Dependent Claim
114 words
A merged bipolar and complementary field effect transistors formed on a semiconductor substrate of a first conductivity type, comprising: a diffused buried DUF region of a second conductivity type formed in a face of said substrate; an epitaxial layer of said second conductivity type formed on a face of said substrate; a plurality of oxide isolation regions formed in said epitaxial layer; a first field effect transistor formed in a first FET one of said oxide isolation regions; a bipolar transistor formed in a bipolar one of said oxide isolation regions above said diffused buried region having an emitter, base, and collector wherein said base has an intrinsic portion and an extrinsic portion of
Claim 25
Dependent Claim
25 words
A device according to claim 21, wherein said first conductivity type is P-type, said second conductivity type is N-type and said semiconductor material is silicon.
Claim 26
Dependent Claim
60 words
A device according to claim 21, including a second diffused buried DUF region of the second conductivity type formed below said first field effect transistor, a P-type channel stop region formed in said substrate, in one of said oxide isolation regions and a second field effect transistor complementary to said first field effect transistor formed over said channel stop region.
Claim 27
Dependent Claim
32 words
A device according to claim 22, wherein said first transistor has P-type source and drain regions, said surrounding channel region is N-type epitaxial region and said DUF region is N⁺ conductivity type.
Claim 28
Dependent Claim
26 words
A device according to claim 23, wherein said second transistor has N-type source and drain regions, and said surrounding channel region is a P⁻-type well region.
Claim 29
Dependent Claim
29 words
A device according to claim 22, wherein said first field effect transistor has P⁺ conductivity type source and drain, and said second transistor has N⁺-conductivity type source and drain.
Claim 30
Dependent Claim
26 words
A device according to claim 22, wherein edges of source/drains of said first and second field effect transistors are spaced apart from associated corresponding isolation regions.
Claim 31
Dependent Claim
51 words
A device according to claim 18, wherein surface contact to the buried diffused DUF region below said bipolar transistor is by a region of N⁺ conductivity type formed by a deep implantation followed by a diffusion so as to reach both said DUF region and a surface of said epitaxial region.
Claim 32
Dependent Claim
14 words
A device according to claim 18, including a surface gettering layer over said device.
Claim 33
Dependent Claim
14 words
A device according to claim 29, wherein the surface gettering layer is phosphosilicate glass.
Claim 34
Dependent Claim
24 words
A device according to claim 25, including a layer of silicide over each of said transistor contacts which interface metal contacts and underlying silicon.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.