US5504018A — Process of fabricating bipolar transistor having …

Claim 1

Independent Claim 311 words

A process of fabricating a bipolar transistor, comprising the steps a) preparing a base structure having a first semiconductor layer of a first conductivity type and a first insulating layer of a first insulating material covering said first semiconductor layer; b) depositing a second semiconductor layer of a second conductivity type opposite to said first conductivity type on said first insulating layer; c) forming a first opening in said second semiconductor layer exposing a part of said first insulating layer; d) covering an upper surface of said second semiconductor layer and an inner wall of said second semiconductor layer defining said first opening with a second insulating layer of a second insulting material; e) etching said first insulating layer by using an etchant having a selectivity between said first insulating material and said second insulating material so as to form a second opening exposing a part of said first semiconductor layer, said second opening being wider than said first opening so that said second semiconductor layer has an overhang portion exposing a lower surface thereof to said second opening; f) epitaxially growing a third semiconductor layer from said lower surface of said second semicondcutor layer and said part of said first semiconductor layer until a space below said overhang portion is filled with a peripheral portion of said third semiconductor layer, said peripheral portion of said third semiconductor layer being thicker than a central portion of said third semiconductor layer below said first opening; g) diffusing a dopant impurity of said second conductivity type from said second semiconductor layer into said peripheral portion so as to form a base rink substructure; h) growing a fourth semiconductor layer of said second conductivity type from said third semiconductor layer so as to form an intrinsic base structure; and i) forming an emitter region of said first conductivity type on said fourth semiconductor layer.

Claim 2

Dependent Claim 311 words

A process of fabricating a bipolar transistor, comprising the steps a) preparing a base structure having a first semiconductor layer of a first conductivity type and a first insulating layer of a first insulating material covering said first semiconductor layer; b) depositing a second semiconductor layer of a second conductivity type opposite to said first conductivity type on said first insulating layer; c) forming a first opening in said second semiconductor layer exposing a part of said first insulating layer; d) covering an upper surface of said second semiconductor layer and an inner wall of said second semiconductor layer defining said first opening with a second insulating layer of a second insulting material; e) etching said first insulating layer by using an etchant having a selectivity between said first insulating material and said second insulating material so as to form a second opening exposing a part of said first semiconductor layer, said second opening being wider than said first opening so that said second semiconductor layer has an overhang portion exposing a lower surface thereof to said second opening; f) epitaxially growing a third semiconductor layer from said lower surface of said second semicondcutor layer and said part of said first semiconductor layer until a space below said overhang portion is filled with a peripheral portion of said third semiconductor layer, said peripheral portion of said third semiconductor layer being thicker than a central portion of said third semiconductor layer below said first opening; g) diffusing a dopant impurity of said second conductivity type from said second semiconductor layer into said peripheral portion so as to form a base rink substructure; h) growing a fourth semiconductor layer of said second conductivity type from said third semiconductor layer so as to form an intrinsic base structure; and i) forming an emitter region of said first conductivity type on said fourth semiconductor layer.

Claim 3

Dependent Claim 77 words

The process as set forth in claim 1, in which said first semiconductor layer and said second semiconductor layer are formed of single crystalline silicon and poly crystalline silicon, respectively, and said third semiconductor layer includes a single crystalline silicon sub-layer grown from said lower surface of said second semiconductor layer and a poly-crystalline silicon sub-layer grown from said part of said first semicondcutor layer and having a peripheral portion merged with said single crystalline silicon sub-layer.

Claim 4

Dependent Claim 31 words

The process as set forth in claim 2, in which said single crystalline silicon sub-layer and said poly-crystalline silicon sub-layer are concurrently grown by an ultra high vacuum chemical vapor deposition.

Claim 5

Dependent Claim 44 words

The process as set forth in claim 3, in which said ultra high vacuum mechanical vapor deposition is carried out by using a reactant gaseous mixture of Si 2 H 6 and Cl 2 and a dopant gas mixed with said reactant gaseous mixture.

Claim 6

Dependent Claim 28 words

The process as set forth in claim 4, in which said reactant gaseous mixture contains Si 2 H 6 of 12 sccm and Cl 2 of 0.04 sccm.

Claim 7

Dependent Claim 125 words

The process as set forth in claim 1, in which said first semiconductor layer and said second semiconductor layer are formed of single crystalline silicon and poly-crystalline silicon, respectively, said third semiconductor layer including a single crystalline silicon sub-layer grown from said lower surface of said second semiconductor layer and a poly-crystalline silicon sub-layer grown from said part of said first semicondcutor layer and having a peripheral portion merged with said single crystalline silicon sub-layer, said fourth semiconductor layer including a lightly doped silicon-germanium layer covering an exposed surface of said single crystalline silicon sub-layer and a heavily doped silicon-germanium layer covering said lightly doped silicon-germanium layer, another exposed surface of said single crystalline silicon sub-layer and an exposed surface of said poly-crystalline silicon layer.

Claim 8

Dependent Claim 71 words

The process as set forth in claim 6, in which said lightly doped silicon-germanium layer and said heavily doped silicon-germanium layer are successively grown by an ultra high vacuum chemical vapor deposition using a reactant gaseous mixture of Si 2 H 6 and GeH 4 and a dopant gas changed in flow rate between a deposition of said lightly doped silicon-germanium layer and a deposition of said heavily doped silicon-germanium layer.

Claim 9

Dependent Claim 47 words

The process as set forth in claim 1, further comprising the step of h-1) forming a buried collector region of said first conductivity type passing through a part of said heavily doped silicon-germanium layer into said first semiconductor layer between said step h) and said step i).

Claim 10

Dependent Claim 71 words

The process as set forth in claim 8, further comprising the step of h-2) forming an insulating side wall on a side wall portion of said fourth semiconductor layer so as to define a third opening between said step h-1) and said step i), said emitter region being formed in said third opening and held in contact with a bottom portion of said fourth semiconductor layer exposed to said third opening.

Claim 11

Dependent Claim 123 words

The process as set forth in claim 1, in which said third semiconductor layer includes a single crystalline semiconductor sub-layer of said first conductivity type grown from said part of said first semiconductor layer and a poly-crystalline semiconductor sub-layer of said first conductivity type grown from said lower surface of said second semiconductor layer, said dopant impurity of said second conductivity type being diffused into said poly-crystalline semiconductor sub-layer and an upper portion of said single crystalline semiconductor sub-layer in said step g), said poly-crystalline semiconductor sub-layer and said upper portion of said single crystalline semiconductor sub-layer forming in combination said base rink structure on a peripheral area of a lower portion of said single crystalline semiconductor sub-layer of said first conductivity type.

Claim 12

Dependent Claim 89 words

The process as set forth in claim 10, in which said fourth semiconductor layer includes a single crystalline lower sub-layer of said second conductivity type grown on a central area of said lower portion of said single crystalline semiconductor sub-layer of said first conductivity type and an inner side surface of said upper portion of said single crystalline semiconductor sub-layer of said second conductivity type and a single crystalline graded upper sub-layer of said second conductivity type grown on said single crystalline lower sub-layer of said second conductivity type.

Claim 13

Dependent Claim 33 words

The process as set forth in claim 11, in which said single crystalline lower sub-layer of said second conductivity type and said single crystalline graded upper sub-layer are formed of a silicon germanium.

Claim 14

Dependent Claim 29 words

The process as set forth in claim 12, in which a germanium content of said single crystalline graded upper sub-layer is varied in a direction of a thickness thereof.

Claim 15

Dependent Claim 106 words

The process as set forth in claim 1, in which said step i) includes the sub-steps of i-1) growing a fifth semiconductor layer on said fourth semiconductor layer, i-2) forming an insulating side wall covering at least said base rink structure and defining a third opening, i-3) forming an emitter electrode in said third opening and held in contact with said fifth semiconductor layer, said emitter electrode containing a dopant impurity of said first conductivity type, and i-4) diffusing said dopant impurity of said first conductivity type from said emitter electrode into a part of said fifth semiconductor layer so as to form said emitter region.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-04-02	1999-10-02	2000-04-02	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-04-02	2003-10-02	2004-04-02	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-04-02	2007-10-02	2008-04-02	$7700.00	Window Closed / Lapsed

Process of fabricating bipolar transistor having epitaxially grown base layer without deterioration of transistor characteristics

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