US5457062A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming gigaohm load for BiCMOS process
Assignee: Texas Instruments Inc
•
Filing: 1994-09-02
•
Granted: 1995-10-10
•
Expires: 2014-09-02
Abstract
Abstract An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.
Inventors
- 👤 Stephen A. Keller
- 👤 Rajiv R. Shah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D88/00; Y; Y10; Y10S; Y10S148/00; Y10S148/136
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
118 words
A method of forming an integrated circuit including a highly resistive amorphous silicon resistor, comprising the steps of: forming a first conductive layer over a substrate; removing portions of said first conductive layer to form a first plate of a capacitor; forming a dielectric layer over said first conductive layer; forming an amorphous silicon layer over said dielectric layer; removing portions of said amorphous silicon layer to define a second amorphous silicon plate of said capacitor and the body of a highly resistive amorphous silicon resistor; forming an insulator layer over a first portion of said highly resistive amorphous silicon resistor; and forming contacts in contact with second and third portions of said highly resistive amorphous silicon resistor.
Claim 2
Independent Claim
118 words
A method of forming an integrated circuit including a highly resistive amorphous silicon resistor, comprising the steps of: forming a first conductive layer over a substrate; removing portions of said first conductive layer to form a first plate of a capacitor; forming a dielectric layer over said first conductive layer; forming an amorphous silicon layer over said dielectric layer; removing portions of said amorphous silicon layer to define a second amorphous silicon plate of said capacitor and the body of a highly resistive amorphous silicon resistor; forming an insulator layer over a first portion of said highly resistive amorphous silicon resistor; and forming contacts in contact with second and third portions of said highly resistive amorphous silicon resistor.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein said step of removing portions of said amorphous silicon layer further includes defining a fuse.
Claim 4
Dependent Claim
35 words
The method of claim 1 and further comprising the steps of: masking portions of said resistor body; and doping said second amorphous silicon plate of said capacitor and the unmasked portions of said resistor body.
Claim 5
Dependent Claim
30 words
The method of claim 2 and further comprising the steps of: masking portions of said fuse; and doping said second amorphous silicon plate and the unmasked portions of said fuse.
Claim 6
Dependent Claim
59 words
The method of claim 4 wherein said doping step comprises doping said second amorphous silicon plate and the unmasked portions of said fuse with a dopant of a first conductivity type and further comprising the step of: masking said fuse and said amorphous silicon second plate; and doping said resistor body with a dopant of a second conductivity type.
Claim 7
Dependent Claim
26 words
The method of claim 1 and further comprising the step of forming a mask over a portion of said substrate in which a diode is formed.
Claim 8
Dependent Claim
38 words
The method of claim 6 and further comprising the steps of siliciding portions of the resistor and said second amorphous silicon plate, the mask over said substrate operable to prevent silicidation over said diode portion of said substrate.
Claim 9
Dependent Claim
38 words
The method of claim 1 wherein said step of removing portions of said first conductive layer further includes the step of defining gates for one or more MOS transistors and polysilicon emitters for one or more bipolar transistors.
Claim 10
Dependent Claim
18 words
The method of claim 3 wherein said doping step further comprises doping source/drain regions for an MOS transistor.
Claim 11
Dependent Claim
19 words
The method of claim 9 wherein said doping step further comprises doping a collector region for a bipolar transistor.
References Cited (Backward Citations)
US4001762A
Cited
US4208781A
Cited
US4408385A
Cited
US4370798A
Cited
US4419812A
Cited
US4682402A
Cited
US4579600A
Cited
US4679170A
Cited
US4737838A
Cited
US4971924A
Cited
US5013678A
Cited
US4762801A
Cited
JPS6471230A
Cited
US5135888A
Cited
US5196233A
Cited
US5047826A
Cited
US5077226A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-09 | 1999-04-10 | 1999-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-09 | 2003-04-10 | 2003-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-09 | 2007-04-10 | 2007-10-10 | $7700.00 | Window Closed / Lapsed |