Manufacturing method for BiCMOS devices

Claim 1

A manufacturing method for BiCMOS device, comprising the steps of: implanting second conductivity ion impurities of high concentration into a predetermined portion of a first conductivity semiconductor substrate; implanting the first conductivity ion impurities of high concentration into a portion interposed between the regions implanted by the second conductivity ion impurities; forming first, second, and third regions by activating the implanted impurities; forming an epitaxial layer on the entire surface of the structure; forming first, second, and third wells on the first, second, and third regions, each being implanted by the same conductivity ion impurities with each region; forming a field oxide layer on the entire surface of the structure to define device regions; forming a second conductivity diffusion layer of high concentration on a predetermined portion of the first well; forming a gate oxide layer on the entire surface of the structure; forming a first polysilicon layer after removing the gate oxide layer from a predetermined portion of the second well, being used as an interconnection line and gates of the first and second MOS transistors on the second and third wells; forming a spacer at sidewalls of the first polysilicon layer; implanting the first conductivity ion impurities of high concentration to form a base contact region in the first well and to form source and drain regions of the first MOS transistor in the third well; implanting the first conductivity ion impurities of low concentration to form a base region in the first well; implanting the second conductivity ion impurities of high concentration at a predetermined form a source and a drain of the second MOS transistor; diffusing the implanted ion impurities; exposing predetermined portions of the first polysilicon layer used for the interconnection line and the base region after forming an oxide layer on the entire surface of the structure; forming an amorphous silicon layer on the exposed portions of the first polysilicon layer and the base region; implanting ion impurities into the amorphous silicon layer except the predetermined prortion of the first polysilicon layer; annealing and oxidizing the amorphous silicon layer to be converted to a second polysilicon layer and simultaneously forming an emitter region; forming a first metal electrode in such a manner that an oxide layer is formed on the entire surface of the structure and a predetermined region thereof is exposed; forming a second metal electrode in such a manner that an oxide layer is formed on the entire surface of the structure and the predetermined electrode of the first MOS transistor is exposed; and forming a protection layer on the entire surface of structure.