US5196233A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating semiconductor circuits
Assignee: STMicroelectronics lnc USA
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Filing: 1989-01-18
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Granted: 1993-03-23
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Expires: 2009-01-18
Abstract
Abstract A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.
Inventors
- 👤 Tsiu C. Chan
- 👤 William A. Bishop
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:52
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/12; H10B10/125; H10D84/00; H10D84/01; H10B10/15
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
179 words
A method for making a resistive load element for a semiconductor integrated circuit device, comprising the steps of: forming a first layer of polycrystalline silicon signal lines over the integrated circuit; forming an insulating layer over the integrated circuit; forming contact openings in the insulating layer, wherein a selected set of such openings expose portions of the first layer of signal lines and an underlying substrate in each opening; forming a second layer of polycrystalline silicon having a first conductivity type over the surface of the integrated circuit; within the second polycrystalline layer, forming regions having a second conductivity type; patterning the second polycrystalline layer to form elongate elements having a region of the first conductivity type between two separate regions of the second conductivity type, wherein current flowing through the element passes successively through second conductivity type, then first conductivity type, then second conductivity type regions, and further wherein the elongate elements make electrical contact with both the underlying substrate and with the exposed first polycrystalline silicon layer portions in the contact openings, thereby forming a shared contact.
Claim 2
Independent Claim
179 words
A method for making a resistive load element for a semiconductor integrated circuit device, comprising the steps of: forming a first layer of polycrystalline silicon signal lines over the integrated circuit; forming an insulating layer over the integrated circuit; forming contact openings in the insulating layer, wherein a selected set of such openings expose portions of the first layer of signal lines and an underlying substrate in each opening; forming a second layer of polycrystalline silicon having a first conductivity type over the surface of the integrated circuit; within the second polycrystalline layer, forming regions having a second conductivity type; patterning the second polycrystalline layer to form elongate elements having a region of the first conductivity type between two separate regions of the second conductivity type, wherein current flowing through the element passes successively through second conductivity type, then first conductivity type, then second conductivity type regions, and further wherein the elongate elements make electrical contact with both the underlying substrate and with the exposed first polycrystalline silicon layer portions in the contact openings, thereby forming a shared contact.
Claim 3
Dependent Claim
53 words
The method of claim 1, wherein said second conductivity type region forming step comprises the steps of: patterning a layer of photoresist over the second polycrystalline silicon layer; and doping exposed regions of the second polycrystalline silicon layer with impurities, which convert the polycrystalline silicon to the second conductivity type, using ion implantation.
Claim 4
Dependent Claim
19 words
The method of claim 2, wherein the first conductivity type is N-type and the second conductivity type is P-type.
Claim 5
Dependent Claim
20 words
The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type. f
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-22 | 1996-09-21 | 1997-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-22 | 2000-09-21 | 2001-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-22 | 2004-09-21 | 2005-03-23 | $7700.00 | Window Closed / Lapsed |