US4367580A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for making polysilicon resistors
Assignee: Texas Instruments Inc
•
Filing: 1980-03-21
•
Granted: 1983-01-11
•
Expires: 2000-03-21
Abstract
Abstract Polycrystalline silicon resistor elements are formed in MOS integrated circuits by a method which requires no additional mask and etch steps other than a standard double-level poly process. The resistors are defined in first level polysilicon which also forms floating gates in FAMOS devices. The resistors are masked by the second level poly which is patterned to define control gates for the FAMOS cells at the same time as the resistor mask is created. The first level poly is implanted at a level which produces the desired resistivity, which is same as the necessary doping level for the floating gates. FAMOS cells are floating gate MOS transistors which are electrically programmable and may also be electrically erasable or electrically alterable.
Inventors
- 👤 Daniel C. Guterman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:22
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10P; H10P32/00; H10P32/30; H10P32/302; H10D88/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
137 words
A method of making a resistor element in an integrated semiconductor device of the type having at least one active circuit element at a face of a semiconductor body, comprising the steps of: depositing a first layer of polycrystalline silicon on said face, introducing conductivity-determining impurity into said first layer to establish a first level of impurity doping therein, patterning said first layer to define a resistor area and a first electrode area for said active circuit element, the resistor area and the first electrode area being spaced from one another on said face, depositing a second layer of conductive material on said face overlying said first layer but insulated therefrom, and patterning said second layer to define a mask area over part of said resistor area and a second electrode area for said active circuit element.
Claim 2
Independent Claim
137 words
A method of making a resistor element in an integrated semiconductor device of the type having at least one active circuit element at a face of a semiconductor body, comprising the steps of: depositing a first layer of polycrystalline silicon on said face, introducing conductivity-determining impurity into said first layer to establish a first level of impurity doping therein, patterning said first layer to define a resistor area and a first electrode area for said active circuit element, the resistor area and the first electrode area being spaced from one another on said face, depositing a second layer of conductive material on said face overlying said first layer but insulated therefrom, and patterning said second layer to define a mask area over part of said resistor area and a second electrode area for said active circuit element.
Claim 3
Dependent Claim
16 words
A method according to claim 1 wherein the second electrode area overlies the first electrode area.
Claim 4
Dependent Claim
28 words
A method according to claim 2 wherein the second layer is polycrystalline silicon and after patterning said second layer a second step of introducing conductivity-determining impurity is performed.
Claim 5
Dependent Claim
48 words
A method according to claim 3 wherein said second step of introducing impurity establishes a second level of impurity doping in contact regions of said resistor area where the resistor area is not covered by said second layer, said second level being much higher than said first level.
Claim 6
Dependent Claim
32 words
A method according to claim 4 wherein said active circuit element is a floating gate electrically programmable memory cell and said first and second electrode areas are floating gate and control gate.
Claim 7
Dependent Claim
22 words
A method according to claim 5 wherein said second step of introducing impurity forms source and drain regions for said memory cell.
References Cited (Backward Citations)
US3984822A
Cited
US4055444A
Cited
US4110776A
Cited
US4208781A
Cited
US4112509A
Cited
US4187602A
Cited
US4209716A
Cited
US4258378A
Cited
US4258466A
Cited
US4246593A
Cited
US4265685A
Cited
US4285117A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-10 | 1986-07-12 | 1987-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-10 | 1990-07-12 | 1991-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-10 | 1994-07-12 | 1995-01-11 | $7700.00 | Window Closed / Lapsed |