US4276543A
Expired / Lapsed
US
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Monolithic triple diffusion analog to digital converter
Assignee: Raytheon Co
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Filing: 1979-03-19
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Granted: 1981-06-30
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Expires: 1999-03-19
Abstract
Abstract A parallel analog-to-digital converter having high speed and high resolution, fabricated on a single integrated-circuit chip in such a manner as to avoid problems typically associated with high speed parallel converters. The converter disclosed by way of example has an eight-bit output, 256 matched comparators for quantizing an analog input signal, and encoding and latching logic for deriving digital outputs from the comparators. Problems related to comparator mismatching, high comparator input capacitance and high comparator input bias current, are effectively minimized by the use of a triple diffusion fabrication process, which substantially reduces the number of defects in the circuit and provides a relatively high component packing density.
Inventors
- 👤 Ralph W. Miller
- 👤 James G. Peterson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:02
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/36; H03M1/361
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
111 words
A monolithic parallel analog-to-digital converter having an n-bit binary output, where n is at least 5, said converter comprising: 2 n-1 comparators; voltage divider means to provide 2 n-1 uniformly graduated reference voltage levels for application to one terminal of each of said comparators; means for coupling an analog input voltage to the other terminal of each of said comparators; and encoding logic means for converting output signals from said comparators to an equivalent n-bit binary signal; and wherein said converter is fabricated in accordance with a high-density triple diffusion process providing a high resolution feature geometry and correspondingly small junction depths, to provide high packing density and high production yield.
Claim 2
Dependent Claim
111 words
A monolithic parallel analog-to-digital converter having an n-bit binary output, where n is at least 5, said converter comprising: 2 n-1 comparators; voltage divider means to provide 2 n-1 uniformly graduated reference voltage levels for application to one terminal of each of said comparators; means for coupling an analog input voltage to the other terminal of each of said comparators; and encoding logic means for converting output signals from said comparators to an equivalent n-bit binary signal; and wherein said converter is fabricated in accordance with a high-density triple diffusion process providing a high resolution feature geometry and correspondingly small junction depths, to provide high packing density and high production yield.
Claim 3
Dependent Claim
20 words
An analog-to-digital converter as set forth in claim 1, wherein said triple diffusion process provides approximately a two-micron feature geometry.
Claim 4
Dependent Claim
23 words
An analog-to-digital converter as set forth in claim 2, wherein said comparators and said encoding logic means include a plurality of NPN transistors.
Claim 5
Dependent Claim
63 words
An analog-to-digital converter as set forth in claim 3, wherein each of said transistors has an N type collector region diffused to a depth of approximately 3.5 microns, a P type base region diffused to a depth of approximately 1.2 microns into said collector region, and an N+ type emitter region diffused to a depth of approximately 0.9 micron into said base region.
Claim 6
Dependent Claim
117 words
A monolithic parallel analog-to-digital converter having a resolution of one part in thirty-two or better, said converter comprising: a substrate on which various circuit elements may be formed by a triple diffusion fabrication process; a plurality of comparators formed on said substrate by the triple diffusion fabrication process, to provide an acceptably high production yield in spite of a large number of required components; a precision voltage divider also formed on said substrate, to provide a plurality of discrete reference voltage levels for connection to said comparators for comparison with an analog voltage level to be converted; and encoding logic also formed on said substrate, to convert output signals from said comparators to an equivalent digital code.
Claim 7
Dependent Claim
117 words
A monolithic parallel analog-to-digital converter having a resolution of one part in thirty-two or better, said converter comprising: a substrate on which various circuit elements may be formed by a triple diffusion fabrication process; a plurality of comparators formed on said substrate by the triple diffusion fabrication process, to provide an acceptably high production yield in spite of a large number of required components; a precision voltage divider also formed on said substrate, to provide a plurality of discrete reference voltage levels for connection to said comparators for comparison with an analog voltage level to be converted; and encoding logic also formed on said substrate, to convert output signals from said comparators to an equivalent digital code.
Claim 8
Dependent Claim
49 words
An analog-to-digital converter as set forth in claim 5, wherein said encoding logic includes: first logic means for generating a 1-in-n code indicative of the analog voltage level, where n is at least 32; and second logic means for generating a multiple-bit binary code equivalent to the 1-in-n code.
Claim 9
Dependent Claim
20 words
An analog-to-digital converter as set forth in claim 5, wherein said triple diffusion process provides approximately a two-micron feature geometry.
Claim 10
Dependent Claim
21 words
An analog-to-digital converter as set forth in claim 7, wherein said comparators and encoding logic include a plurality of NPN transistors.
Claim 11
Dependent Claim
63 words
An analog-to-digital converter as set forth in claim 8, wherein each of said transistors has an N type collector region diffused to a depth of approximately 3.5 microns, a P type base region diffused to a depth of approximately 1.2 microns into said collector region, and an N+ type emitter region diffused to a depth of approximately 0.9 micron into said base region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-06-29 | 1984-12-29 | 1985-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-06-29 | 1988-12-29 | 1989-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-06-29 | 1992-12-29 | 1993-06-30 | $7700.00 | Window Closed / Lapsed |