Bipolar transistor construction method

Claim 1

A method of fabricating an integrated circuit array of bipolar transistors utilizing a triple diffusion process, comprising: a. forming on a semiconductor substrate surface of first conductivity type a permanent masking layer of substantial thickness defining a multiplicity of rectangular openings of width S and length 6S, where S equals about 0.1 mil, with each opening surrounded by a rectangular masking region of width S, and with adjacent masking regions separated from each other by a continuous unmasked region of width S, said rectangular opening being capable of division into six zones of equal area arranged in a row and identified as zones 1 through 6 taken consecutively; b. applying a first masking layer of etchable material substantially thinner than said permanent masking layer over the surface of said substrate defined by said continuous region; c. diffusing an impurity of second conductivity type into surface regions of said substrate defined by all six zones of said rectangular openings to form collector regions within said substrate; d. applying a second masking layer of said etchable material over the surface of said substrate defined by all six zones of said rectangular openings; e. etching said etchable material from said continuous region and from zones 3 through 6 of said rectangular openings; f. diffusing an impurity of said first conductivity type into surface regions of said substrate defined by said continuous region and said zones 3 through 6 of said rectangular openings to form isolation regions surrounding all of the collector regions of said array and to form base regions within said collector regions; g. applying a third masking layer of said etchable material over the surface of said substrate defined by said continuous region and said zones 3 through 6 of said rectangular openings; h. etching said etchable material from zones 1 and 6 of said rectangular openings; i. diffusing an impurity of said second conductivity type into surface regions of said substrate defined by said zones 1 and 6 of said rectangular openings to form collector contact regions within said collector regions and emitter regions within said base regions; j. applying a fourth masking layer of said etchable material over the surface of said substrate defined by said zones 1 and 6 of said rectangular openings; k. etching said etchable material from zones 1, 4, and 6 of said rectangular openings; and l. depositing metal through said zones 1, 4, and 6 of said rectangular openings to form metallic contacts to said collector contact, base, and emitter regions, respectively.

Claim 2

A method of fabricating an integrated circuit array of bipolar transistors utilizing a triple diffusion process, comprising: a. forming on a semiconductor substrate surface of first conductivity type a permanent masking layer of substantial thickness defining a multiplicity of rectangular openings of width S and length 6S, where S equals about 0.1 mil, with each opening surrounded by a rectangular masking region of width S, and with adjacent masking regions separated from each other by a continuous unmasked region of width S, said rectangular opening being capable of division into six zones of equal area arranged in a row and identified as zones 1 through 6 taken consecutively; b. applying a first masking layer of etchable material substantially thinner than said permanent masking layer over the surface of said substrate defined by said continuous region; c. diffusing an impurity of second conductivity type into surface regions of said substrate defined by all six zones of said rectangular openings to form collector regions within said substrate; d. applying a second masking layer of said etchable material over the surface of said substrate defined by all six zones of said rectangular openings; e. etching said etchable material from said continuous region and from zones 3 through 6 of said rectangular openings; f. diffusing an impurity of said first conductivity type into surface regions of said substrate defined by said continuous region and said zones 3 through 6 of said rectangular openings to form isolation regions surrounding all of the collector regions of said array and to form base regions within said collector regions; g. applying a third masking layer of said etchable material over the surface of said substrate defined by said continuous region and said zones 3 through 6 of said rectangular openings; h. etching said etchable material from zones 1 and 6 of said rectangular openings; i. diffusing an impurity of said second conductivity type into surface regions of said substrate defined by said zones 1 and 6 of said rectangular openings to form collector contact regions within said collector regions and emitter regions within said base regions; j. applying a fourth masking layer of said etchable material over the surface of said substrate defined by said zones 1 and 6 of said rectangular openings; k. etching said etchable material from zones 1, 4, and 6 of said rectangular openings; and l. depositing metal through said zones 1, 4, and 6 of said rectangular openings to form metallic contacts to said collector contact, base, and emitter regions, respectively.