US6048763A — Integrated capacitor bottom electrode with etch s…

Claim 1

Independent Claim 105 words

A process for forming a bottom electrode for an integrated capacitor, comprising: forming at least one gate electrode over a semiconductor substrate, the gate electrode covered with insulating material; forming an etch stop layer over the insulating material covering the gate electrode and over an active area within the substrate and adjacent the gate electrode; forming a sacrificial layer over the etch stop layer; etching a contact hole over the active area through the sacrificial layer selectively against the etch stop layer; removing the etch stop layer from over the active area in the contact hole; forming a capacitor bottom electrode in said contact hole.

Claim 2

Dependent Claim 105 words

A process for forming a bottom electrode for an integrated capacitor, comprising: forming at least one gate electrode over a semiconductor substrate, the gate electrode covered with insulating material; forming an etch stop layer over the insulating material covering the gate electrode and over an active area within the substrate and adjacent the gate electrode; forming a sacrificial layer over the etch stop layer; etching a contact hole over the active area through the sacrificial layer selectively against the etch stop layer; removing the etch stop layer from over the active area in the contact hole; forming a capacitor bottom electrode in said contact hole.

Claim 3

Dependent Claim 17 words

The process of claim 1, wherein said bottom electrode is in direct contact with the active area.

Claim 4

Dependent Claim 32 words

The process of claim 1, further comprising forming a planar masking layer over the sacrificial layer and etching the contact hole through the masking layer prior to etching through the sacrificial layer.

Claim 5

Dependent Claim 26 words

The process of claim 1, wherein forming the etch stop layer comprises depositing a layer of substantially uniform thickness between about 50 Å and 2,000 Å.

Claim 6

Dependent Claim 20 words

The process of claim 4, wherein the etch stop layer thickness is uniform within about ±10% of an average thickness.

Claim 7

Dependent Claim 20 words

The process of claim 5, wherein the etch stop layer thickness is uniform within about ±3% of the average thickness.

Claim 8

Dependent Claim 24 words

The process of claim 1, wherein forming the etch stop layer comprises depositing a material resistant to an etchant which etches the sacrificial layer.

Claim 9

Dependent Claim 19 words

The process of claim 7, wherein the etch stop layer comprises silicon oxide and the sacrificial layer comprises polysilicon.

Claim 10

Dependent Claim 24 words

The process of claim 7, wherein the etchant selectively etches the sacrifical layer with greater than about 10:1 selectivity over the etch stop layer.

Claim 11

Dependent Claim 15 words

The process of claim 8, wherein removing the etch stop layer comprises a timed etch.

Claim 12

Dependent Claim 15 words

The process of claim 10, wherein removing the etch stop layer comprises a selective etch.

Claim 13

Dependent Claim 52 words

The process of claim 1, wherein forming the bottom electrode comprises: depositing a conductive layer to form a conductive container lining the contact hole and a conductive top layer overlying a portion of the sacrificial layer remaining after etching the contact hole; and removing the conductive top layer overlying the sacrificial layer.

Claim 14

Dependent Claim 26 words

The process of claim 12, wherein forming the bottom electrode further comprises removing the remaining sacrificial layer to expose an outside surface of the conductive container.

Claim 15

Dependent Claim 15 words

The process of claim 12, wherein removing the conductive top layer comprises a mechanical planarization.

Claim 16

Dependent Claim 14 words

The process of claim 14, wherein the mechanical planarization comprises a chemical mechanical planarization.

Claim 17

Dependent Claim 153 words

A process for fabricating a memory cell capacitor in a semiconductor substrate comprising: providing at least one conductive word line on a surface of the substrate, wherein the word line is effectively isolated by isolation spacers and wherein an active area within the substrate is positioned adjacent the word line; positioning a multilayer structure on the word lines and the active areas, the multilayer structure comprising at least two layers having different characteristic etch rates with respect to at least one etching process; selectively etching a first portion of the multilayer structure to define a capacitor container region; removing a second portion of the multilayer structure remaining within the container region after selectively etching the first portion, thereby exposing the active area; and depositing a first conductive layer into the container region in direct contact with the exposed active area, the first conductive layer forming a bottom electrode of the memory cell capacitor.

Claim 18

Dependent Claim 153 words

A process for fabricating a memory cell capacitor in a semiconductor substrate comprising: providing at least one conductive word line on a surface of the substrate, wherein the word line is effectively isolated by isolation spacers and wherein an active area within the substrate is positioned adjacent the word line; positioning a multilayer structure on the word lines and the active areas, the multilayer structure comprising at least two layers having different characteristic etch rates with respect to at least one etching process; selectively etching a first portion of the multilayer structure to define a capacitor container region; removing a second portion of the multilayer structure remaining within the container region after selectively etching the first portion, thereby exposing the active area; and depositing a first conductive layer into the container region in direct contact with the exposed active area, the first conductive layer forming a bottom electrode of the memory cell capacitor.

Claim 19

Dependent Claim 27 words

The process of claim 16, further comprising removing a third portion of the multilayer structure remaining outside of the container region after depositing the first conductive layer.

Claim 20

Dependent Claim 26 words

The process of claim 16, further comprising positioning and patterning a first photoresist mask layer over the multilayer structure prior to selectively etching the first portion.

Claim 21

Dependent Claim 57 words

The process of claim 16, wherein positioning the multilayer structure comprises: depositing an etch stop layer capable of protecting the isolation spacers and the active area from damage from selectively etching the first portion of the multilayer section; depositing a sacrificial layer on the etch stop layer; and depositing a mask layer on the conductive material layer.

Claim 22

Dependent Claim 186 words

A process for fabricating a memory cell capacitor in an integrated circuit, comprising: providing at least one conductive word line on a semiconductor substrate adjacent an active area within the substrate, wherein said word-lines are effectively isolated by isolation spacers; depositing a conformal etch stop layer over the word line and the active area; depositing a sacrificial layer over the etch stop layer; depositing a mask layer over the sacrificial layer; selectively removing a portion of the mask layer and selectively etching a portion of the sacrificial layer to define a capacitor region above the active area while leaving the etch stop layer covering the isolation spacers and the active area; selectively removing a portion of the etch stop layer to expose the active area; depositing a first conductive layer over the capacitor region; selectively removing a portion of the conductive layer to form a storage plate layer within the capacitor region; depositing a dielectric layer over the storage plate layer; depositing a second conductive layer over the dielectric layer; and selectively removing a portion of the second conductive layer to form a reference plate layer.

Claim 23

Dependent Claim 186 words

A process for fabricating a memory cell capacitor in an integrated circuit, comprising: providing at least one conductive word line on a semiconductor substrate adjacent an active area within the substrate, wherein said word-lines are effectively isolated by isolation spacers; depositing a conformal etch stop layer over the word line and the active area; depositing a sacrificial layer over the etch stop layer; depositing a mask layer over the sacrificial layer; selectively removing a portion of the mask layer and selectively etching a portion of the sacrificial layer to define a capacitor region above the active area while leaving the etch stop layer covering the isolation spacers and the active area; selectively removing a portion of the etch stop layer to expose the active area; depositing a first conductive layer over the capacitor region; selectively removing a portion of the conductive layer to form a storage plate layer within the capacitor region; depositing a dielectric layer over the storage plate layer; depositing a second conductive layer over the dielectric layer; and selectively removing a portion of the second conductive layer to form a reference plate layer.

Claim 24

Dependent Claim 33 words

The process of claim 20, further comprising positioning and patterning a first photoresist mask layer over the mask layer prior to selectively removing the portion of the mask layer and the sacrificial layer.

Claim 25

Dependent Claim 32 words

The process of claim 20, further comprising positioning and patterning a second photoresist mask layer over the second conductive layer prior to the selectively removing the portion of the second conductive layer.

Claim 26

Dependent Claim 13 words

The process of claim 20, wherein the etch stop layer comprises silicon dioxide.

Claim 27

Dependent Claim 13 words

The process of claim 20, wherein the sacrificial layer comprises conductively doped polysilicon.

Claim 28

Dependent Claim 14 words

The process of claim 20, wherein the mask layer comprises borophosphosilicate glass (BPSG) material.

Claim 29

Dependent Claim 110 words

A process for forming an integrated capacitor in a memory array, comprising no more than two photolithographic masking steps, the process comprising: forming a container-shaped contact opening within a structural layer through a first photolithographic mask, a bottom surface of the contact opening comprising an exposed surface of a semiconductor substrate; forming a bottom electrode conductive layer lining the contact opening and over the structural layer; planarizing a portion of the conductive layer overlying the structural layer, thereby forming an electrically isolated bottom electrode container within the contact opening; forming a cell dielectric layer over the bottom electrode; and forming an upper electrode conductive layer over the cell dielectric layer.

Claim 30

Dependent Claim 110 words

A process for forming an integrated capacitor in a memory array, comprising no more than two photolithographic masking steps, the process comprising: forming a container-shaped contact opening within a structural layer through a first photolithographic mask, a bottom surface of the contact opening comprising an exposed surface of a semiconductor substrate; forming a bottom electrode conductive layer lining the contact opening and over the structural layer; planarizing a portion of the conductive layer overlying the structural layer, thereby forming an electrically isolated bottom electrode container within the contact opening; forming a cell dielectric layer over the bottom electrode; and forming an upper electrode conductive layer over the cell dielectric layer.

Claim 31

Dependent Claim 15 words

The process of claim 26, further comprising etching portions of the upper electrode conductive layer.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2003-04-11	2003-10-11	2004-04-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2007-04-11	2007-10-11	2008-04-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2011-04-11	2011-10-11	2012-04-11	$7700.00	Window Closed / Lapsed

Integrated capacitor bottom electrode with etch stop layer

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