US5700349A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming multi-layer interconnections
Assignee: Sony Corp
•
Filing: 1996-01-16
•
Granted: 1997-12-23
•
Expires: 2016-01-16
Abstract
Abstract A method of forming a multi-layer interconnection in which through-holes are formed in an interlayer insulating layer positioned between two neighboring mid interconnection layers, which through-hole is used for establishing an electrical interconnection between upper and lower interconnection layers, comprising the steps of forming an offset insulating film on said mid interconnection layer such that the patterns of the mid interconnection layer and the offset insulating film are the same; forming a sidewall insulating film on the lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film; substantially conformally forming an etch stop layer covering the entire surface of the substrate, said etching stop layer being slower in etch rate than said interlayer insulating film; anisotropically etching said interlayer insulating film in a region having an opening size smaller than the spacing between the interconnecting layers; selectively removing the etching stop layer exposed on the bottom surface of said region for completing the through-hole; and filling said through-hole with an electrically conductive material.
Inventors
- 👤 Masanori Tsukamoto
- 👤 Tetsuo Gocho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:04
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10W20/071; H10W20/074; H10W20/077
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
204 words
A method of forming a semiconductor device having a multi-layer interconnection in which through-holes are formed in an interlayer insulating layer positioned between two neighboring mid interconnection layers, which through-holes are used for establishing an electrical interconnection between upper and lower interconnection layers, comprising the steps of: forming an offset insulating film on said mid interconnection layer such that the patterns of the mid interconnection layer and the offset insulating film are the same; forming a sidewall insulating film on a lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film; substantially conformally forming an etching stop layer covering the entire surface of the semiconductor device, said etching stop layer being slower in etch rate than said interlayer insulating layer; forming the insulating film so as to be substantially planer and so as to cover the entire surface of said semiconductor device for completing a through hole; and anisotropically etching said interlayer insulating layer in a region having an opening size smaller than the spacing between the interconnecting layers; selectively removing the etching stop layer exposed on the bottom surface of said region for completing the through-hole; and filling said through-hole with an electrically conductive material.
Claim 2
Independent Claim
204 words
A method of forming a semiconductor device having a multi-layer interconnection in which through-holes are formed in an interlayer insulating layer positioned between two neighboring mid interconnection layers, which through-holes are used for establishing an electrical interconnection between upper and lower interconnection layers, comprising the steps of: forming an offset insulating film on said mid interconnection layer such that the patterns of the mid interconnection layer and the offset insulating film are the same; forming a sidewall insulating film on a lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film; substantially conformally forming an etching stop layer covering the entire surface of the semiconductor device, said etching stop layer being slower in etch rate than said interlayer insulating layer; forming the insulating film so as to be substantially planer and so as to cover the entire surface of said semiconductor device for completing a through hole; and anisotropically etching said interlayer insulating layer in a region having an opening size smaller than the spacing between the interconnecting layers; selectively removing the etching stop layer exposed on the bottom surface of said region for completing the through-hole; and filling said through-hole with an electrically conductive material.
Claim 3
Dependent Claim
72 words
The method as claim in claim 1, wherein said interlayer insulating layer is formed of an SiO x based material and wherein said etching stop layer is formed using at least one insulating material selected from the group consisting of an Si x N y based material, an Si x O y N z based material and an Al x O y based material, wherein x, y and z are whole numbers.
Claim 4
Dependent Claim
24 words
The method as claimed in claim 1, wherein the opening size of said through-hole is 1 to 1.2 times the applicable minimum processing size.
Claim 5
Dependent Claim
30 words
The method as claimed in claim 1, wherein the mid interconnection layer and the lower interconnection layer are a gate electrode and a source/drain region of a MOS transistor, respectively.
Claim 6
Dependent Claim
21 words
The method as claimed in claim 1, wherein said electrically conductive material is the same material of the upper interconnection layer.
Claim 7
Dependent Claim
16 words
The method as claimed in claim 1, wherein said electrically conductive material comprises an Al-based material.
Claim 8
Dependent Claim
21 words
The method as claimed in claim 1, wherein said electrically conductive material is different than that of the upper interconnection layer.
Claim 9
Dependent Claim
15 words
The method as claimed in claim 7, wherein said electrically conductive material comprises a W-plug.
Claim 10
Dependent Claim
23 words
The method as claimed in claim 1, further comprising a step of forming a film in the through-hole to obtain an excellent coverage.
Claim 11
Independent Claim
166 words
A method for forming a semiconductor device having a multi-layer interconnection by forming a through-hole by boring through an interlayer insulating film in a spacing between interconnection layers of two neighboring mid interconnection layers for establishing electrical conduction between an upper interconnection layer and a lower interconnection layer via said through-hole, comprising the steps of: forming an offset insulating film on said mid interconnection layer with the same pattern as the mid interconnection layer; forming a sidewall insulating film on the lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film, said sidewall insulating film being slower in etch rate than said interlayer insulating film; forming the interlayer insulating film so as to be substantially planar and so as to cover the entire surface of said semiconductor device for completing a through-hole; and anisotropically etching said interlayer insulating layer in an opening size smaller than the spacing between the interconnecting; filling said through-hole with an electrically conductive material.
Claim 12
Independent Claim
166 words
A method for forming a semiconductor device having a multi-layer interconnection by forming a through-hole by boring through an interlayer insulating film in a spacing between interconnection layers of two neighboring mid interconnection layers for establishing electrical conduction between an upper interconnection layer and a lower interconnection layer via said through-hole, comprising the steps of: forming an offset insulating film on said mid interconnection layer with the same pattern as the mid interconnection layer; forming a sidewall insulating film on the lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film, said sidewall insulating film being slower in etch rate than said interlayer insulating film; forming the interlayer insulating film so as to be substantially planar and so as to cover the entire surface of said semiconductor device for completing a through-hole; and anisotropically etching said interlayer insulating layer in an opening size smaller than the spacing between the interconnecting; filling said through-hole with an electrically conductive material.
Claim 13
Dependent Claim
69 words
The method as claimed in claim 10, wherein said interlayer insulating film is formed of an SiO x based material and wherein said sidewall insulating film is formed of at least one insulating material selected from among an Si x N y based material, an Si x O y N z based material and an Al x O y based material, wherein x, y and z are whole numbers.
Claim 14
Dependent Claim
24 words
The method as claimed in claim 10, wherein the opening size of said through-hole is 1 to 1.2 times the applicable minimum processing size.
Claim 15
Dependent Claim
30 words
The method as claimed in claim 10, wherein the mid interconnection layer and the lower interconnection layer are a gate electrode and a source/drain region of a MOS transistor, respectively.
Claim 16
Dependent Claim
22 words
The method as claimed in claim 10, wherein said electrically conductive material is the same as that of the upper interconnection layer.
Claim 17
Dependent Claim
21 words
The method as claimed in claim 10, wherein said electrically conductive material is different than that of the upper interconnection material.
Claim 18
Dependent Claim
23 words
The method as claimed in claim 10, further comprising a step of forming a film in the through-hole to obtain an excellent coverage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-22 | 2001-06-23 | 2001-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-22 | 2005-06-23 | 2005-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-22 | 2009-06-23 | 2009-12-23 | $7700.00 | Window Closed / Lapsed |