Spin-on-glass integration planarization having siloxane partial etchback and silicate processes

Claim 1

The method of planarizing the dielectric layers between conductor layers in submicron integrated circuits without the incorporation of voids and etch encroachment of a conductive layer comprising: providing semiconductor device structures in and on a semiconductor substrate; providing at least one patterned conductive layer for contacting the active elements of said device structures; the surface of said patterned conductive layer structure is irregular with horizontal and vertical components; providing a layer of an insulator over said irregular structure patterned conductive layer; said insulator layer is deposited upon the said irregular structure with horizontal and vertical components and the sidewall thickness of said insulator layer covering said vertical components is equal to 0.6 times the surface thickness of said insulator layer on said horizontal components and furthermore, the space between adjoining insulator sidewalls wherein the size of said space equals the feature size minus two times said sidewall thickness must be greater than or equal to 0.3 microns so that said space can be filled by said siloxane spin-on-glass; covering said insulator layer with at least one siloxane spin-on-glass layer to fill the valleys of said irregular structure and baking to drive off volatile components but not curing said siloxane spin-on-glass layer; partially etching the thickness of said siloxane spin-on-glass layer and the said insulator layer at the top points of said conductive layer while leaving the said siloxane layer in said valleys and avoiding said etch encroachment of said conductive layer; covering said partially etched back siloxane spin-on-glass layer with a silicate spin-on-glass layer and baking said silicate spin-on-glass layer to drive off volatile components; curing both said siloxane and said silicate spin-on-glass layers; and depositing top dielectric layer over said silicate spin-on-glass layer to complete said planarization.

Claim 2

The method of planarizing the dielectric layers between conductor layers in submicron integrated circuits without the incorporation of voids and etch encroachment of a conductive layer comprising: providing semiconductor device structures in and on a semiconductor substrate; providing at least one patterned conductive layer for contacting the active elements of said device structures; the surface of said patterned conductive layer structure is irregular with horizontal and vertical components; providing a layer of an insulator over said irregular structure patterned conductive layer; said insulator layer is deposited upon the said irregular structure with horizontal and vertical components and the sidewall thickness of said insulator layer covering said vertical components is equal to 0.6 times the surface thickness of said insulator layer on said horizontal components and furthermore, the space between adjoining insulator sidewalls wherein the size of said space equals the feature size minus two times said sidewall thickness must be greater than or equal to 0.3 microns so that said space can be filled by said siloxane spin-on-glass; covering said insulator layer with at least one siloxane spin-on-glass layer to fill the valleys of said irregular structure and baking to drive off volatile components but not curing said siloxane spin-on-glass layer; partially etching the thickness of said siloxane spin-on-glass layer and the said insulator layer at the top points of said conductive layer while leaving the said siloxane layer in said valleys and avoiding said etch encroachment of said conductive layer; covering said partially etched back siloxane spin-on-glass layer with a silicate spin-on-glass layer and baking said silicate spin-on-glass layer to drive off volatile components; curing both said siloxane and said silicate spin-on-glass layers; and depositing top dielectric layer over said silicate spin-on-glass layer to complete said planarization.

Claim 8

The method of planarizing the surfaces of a submicron integrated circuit without the incorporation of voids and etch encroachment of a conductive layer comprising: providing a thin insulator layer over said conductive layer which connects devices within said integrated circuit wherein there are substantial surface irregularities; said thin insulator layer is deposited upon the said surface irregularities having vertical and horizontal components and the sidewall thickness of said insulator layer covering the vertical components is equal to 0.6 times the surface thickness of said insulator layer on the horizontal components and furthermore, the space between adjoining insulator sidewalls wherein the size of said space equals the feature size minus two times said sidewall thickness must be greater than or equal to 0.3 microns so that said space can be filled by said siloxane spin-on-glass; covering said thin insulator layer with at least one siloxane spin-on-glass layer to fill the valleys of the said irregularities and baking but not curing said siloxane spin-on-glass layer; partially blanket anisotropically etching said siloxane spin-on-glass layer through its thickness and the thickness of said insulator layer to underlying metal layer at its highest points and leaving the siloxane layer portions in said valleys; covering said partially etched back siloxane spin-on-glass layer with a silicate spin-on-glass layer and baking said silicate spin-on-glass layer; curing both said siloxane and said silicate spin-on-glass layers; and depositing top dielectric layer over said silicate spin-on-glass layer to complete said planarization.

Claim 9

The method of planarizing the surfaces of a submicron integrated circuit without the incorporation of voids and etch encroachment of a conductive layer comprising: providing a thin insulator layer over said conductive layer which connects devices within said integrated circuit wherein there are substantial surface irregularities; said thin insulator layer is deposited upon the said surface irregularities having vertical and horizontal components and the sidewall thickness of said insulator layer covering the vertical components is equal to 0.6 times the surface thickness of said insulator layer on the horizontal components and furthermore, the space between adjoining insulator sidewalls wherein the size of said space equals the feature size minus two times said sidewall thickness must be greater than or equal to 0.3 microns so that said space can be filled by said siloxane spin-on-glass; covering said thin insulator layer with at least one siloxane spin-on-glass layer to fill the valleys of the said irregularities and baking but not curing said siloxane spin-on-glass layer; partially blanket anisotropically etching said siloxane spin-on-glass layer through its thickness and the thickness of said insulator layer to underlying metal layer at its highest points and leaving the siloxane layer portions in said valleys; covering said partially etched back siloxane spin-on-glass layer with a silicate spin-on-glass layer and baking said silicate spin-on-glass layer; curing both said siloxane and said silicate spin-on-glass layers; and depositing top dielectric layer over said silicate spin-on-glass layer to complete said planarization.