Method of making a fully used tub DRAM cell

Claim 1

A method for fabricating a dynamic random access memory (DRAM) having a capacitor comprising: forming field oxide regions in and on a semiconductor substrate; forming a gate silicon oxide layer over the surface of said semiconductor substrate; depositing a gate polysilicon layer overlaying said gate silicon oxide layer and patterning said gate polysilicon to form gate electrodes; forming lightly doped drain regions within said silicon substrate; depositing and etching a spacer silicon oxide to form spacers on the sidewalls of said gate electrodes; forming a first layer of silicon oxide overlying said gate electrodes; depositing a layer of silicon nitride overlaying said first silicon oxide layer; forming a second layer of silicon oxide overlying said silicon nitride layer; opening a contact through said first and second silicon oxide layers and said silicon nitride layer to said lightly doped drain region within said silicon substrate which will form the node of said capacitor; depositing a first layer of doped polysilicon overlying said silicon nitride layer and filling said contact opening wherein portion of said first polysilicon contacting said lightly doped drain region which forms said node will be the bottom electrode of said capacitor; depositing a third layer of silicon oxide overlying said first polysilicon layer; etching away said third layer of silicon oxide overlying said first polysilicon layer; etching away said third layer of silicon oxide leaving portion only within area of planned said capacitor; depositing a second layer of polysilicon overlying said third silicon oxide layer; anisotropically etching said first and second polysilicon layers to remove all of said second polysilicon layer except for spacers on the sidewalls of said third silicon oxide layer to construct a tub shape and to remove all of said first polysilicon layer except for portion underlying said third silicon oxide layer and said spacers; etching away said second silicon oxide layer and said third silicon oxide layer leaving cavities underlying said first and second polysilicon layers wherein said first and second polysilicon layers form the storage node of said capacitor; depositing a capacitor dielectric layer over all surfaces of said substrate wherein said capacitor dielectric layer will cover exposed top and bottom surfaces of said first and second polysilicon layers; depositing a third polysilicon layer conformally so that said third polysilicon layer covers said first and second polysilicon layers and fills all said cavities underlying said first and second polysilicon layers wherein said third polysilicon layer forms the top electrode of said capacitor; depositing a first insulating layer over the surface of said substrate and reflowing said insulator by thermal treatment; depositing a fourth layer of doped polysilicon overlying said first insulating layer; forming a silicide layer over said fourth polysilicon layer; depositing a second insulating layer over said silicide layer and reflowing said insulator by thermal treatment; forming N+ regions in said lightly doped drain regions by outdiffusing dopants from the overlying doped polysilicon layers during said reflowing of said first and second insulating layers; opening contact holes through said second insulating layer to said silicide layer; and depositing a metal layer into said contact holes to form contacts to said silicide layer to complete formation of said DRAM with capacitor.

Claim 2

A method for fabricating a dynamic random access memory (DRAM) having a capacitor comprising: forming field oxide regions in and on a semiconductor substrate; forming a gate silicon oxide layer over the surface of said semiconductor substrate; depositing a gate polysilicon layer overlaying said gate silicon oxide layer and patterning said gate polysilicon to form gate electrodes; forming lightly doped drain regions within said silicon substrate; depositing and etching a spacer silicon oxide to form spacers on the sidewalls of said gate electrodes; forming a first layer of silicon oxide overlying said gate electrodes; depositing a layer of silicon nitride overlaying said first silicon oxide layer; forming a second layer of silicon oxide overlying said silicon nitride layer; opening a contact through said first and second silicon oxide layers and said silicon nitride layer to said lightly doped drain region within said silicon substrate which will form the node of said capacitor; depositing a first layer of doped polysilicon overlying said silicon nitride layer and filling said contact opening wherein portion of said first polysilicon contacting said lightly doped drain region which forms said node will be the bottom electrode of said capacitor; depositing a third layer of silicon oxide overlying said first polysilicon layer; etching away said third layer of silicon oxide overlying said first polysilicon layer; etching away said third layer of silicon oxide leaving portion only within area of planned said capacitor; depositing a second layer of polysilicon overlying said third silicon oxide layer; anisotropically etching said first and second polysilicon layers to remove all of said second polysilicon layer except for spacers on the sidewalls of said third silicon oxide layer to construct a tub shape and to remove all of said first polysilicon layer except for portion underlying said third silicon oxide layer and said spacers; etching away said second silicon oxide layer and said third silicon oxide layer leaving cavities underlying said first and second polysilicon layers wherein said first and second polysilicon layers form the storage node of said capacitor; depositing a capacitor dielectric layer over all surfaces of said substrate wherein said capacitor dielectric layer will cover exposed top and bottom surfaces of said first and second polysilicon layers; depositing a third polysilicon layer conformally so that said third polysilicon layer covers said first and second polysilicon layers and fills all said cavities underlying said first and second polysilicon layers wherein said third polysilicon layer forms the top electrode of said capacitor; depositing a first insulating layer over the surface of said substrate and reflowing said insulator by thermal treatment; depositing a fourth layer of doped polysilicon overlying said first insulating layer; forming a silicide layer over said fourth polysilicon layer; depositing a second insulating layer over said silicide layer and reflowing said insulator by thermal treatment; forming N+ regions in said lightly doped drain regions by outdiffusing dopants from the overlying doped polysilicon layers during said reflowing of said first and second insulating layers; opening contact holes through said second insulating layer to said silicide layer; and depositing a metal layer into said contact holes to form contacts to said silicide layer to complete formation of said DRAM with capacitor.

Claim 16

A method for fabricating a dynamic random access memory having a capacitor comprising: selectively forming field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of semiconductor devices; forming device structures within said device areas of said semiconductor substrate wherein said device structures include a capacitor node contact region within said silicon substrate; forming a first oxide layer over said device and field oxide areas; and forming said capacitors by: depositing a layer of silicon nitride overlying said first silicon oxide layer; forming a second layer of silicon oxide overlying said silicon nitride layer; opening a contact through said first and second silicon oxide layers and said silicon nitride layer to said capacitor node contact region; depositing a first layer of polysilicon overlying said silicon nitride layer and filling said contact opening; depositing a third layer of silicon oxide overlying said first polysilicon layer; patterning said third layer of silicon oxide so as to leave remaining portions of said layer only in the area of planned said capacitor; depositing a second layer of polysilicon overlying said third silicon oxide layer; anisotropically etching said first and second polysilicon layers to remove all of said second layer except for spacers on the sidewalls of said third silicon oxide layer to construct a tub shape and to remove all of said first polysilicon layer except for portions of said layer underlying said third oxide layer and underlying said spacers; etching away said second silicon oxide layer and said third silicon oxide layer leaving cavities underlying said first and second polysilicon layers; depositing a capacitor dielectric layer over all exposed surfaces of said substrate; depositing a third polysilicon layer conformally so that said third polysilicon layer covers said first and second polysilicon layers and fills all said cavities underlying said first and second polysilicon layers wherein said third polysilicon layer can be connected as the top electrode of the capacitor; depositing a first insulating layer over the surface of said substrate and reflowing said insulator by thermal treatment; depositing a fourth layer of polysilicon in contact with the third layer of polysilicon said first insulating layer; forming a silicide layer over said fourth polysilicon layer; depositing a second insulating layer over said silicide layer and reflowing said insulator by thermal treatment; opening contact holes through said insulating layers to said silicide layer; and depositing a metal layer into said contact holes to form contacts to said silicide layer to complete formation of said DRAM with capacitor.

Claim 17

A method for fabricating a dynamic random access memory having a capacitor comprising: selectively forming field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of semiconductor devices; forming device structures within said device areas of said semiconductor substrate wherein said device structures include a capacitor node contact region within said silicon substrate; forming a first oxide layer over said device and field oxide areas; and forming said capacitors by: depositing a layer of silicon nitride overlying said first silicon oxide layer; forming a second layer of silicon oxide overlying said silicon nitride layer; opening a contact through said first and second silicon oxide layers and said silicon nitride layer to said capacitor node contact region; depositing a first layer of polysilicon overlying said silicon nitride layer and filling said contact opening; depositing a third layer of silicon oxide overlying said first polysilicon layer; patterning said third layer of silicon oxide so as to leave remaining portions of said layer only in the area of planned said capacitor; depositing a second layer of polysilicon overlying said third silicon oxide layer; anisotropically etching said first and second polysilicon layers to remove all of said second layer except for spacers on the sidewalls of said third silicon oxide layer to construct a tub shape and to remove all of said first polysilicon layer except for portions of said layer underlying said third oxide layer and underlying said spacers; etching away said second silicon oxide layer and said third silicon oxide layer leaving cavities underlying said first and second polysilicon layers; depositing a capacitor dielectric layer over all exposed surfaces of said substrate; depositing a third polysilicon layer conformally so that said third polysilicon layer covers said first and second polysilicon layers and fills all said cavities underlying said first and second polysilicon layers wherein said third polysilicon layer can be connected as the top electrode of the capacitor; depositing a first insulating layer over the surface of said substrate and reflowing said insulator by thermal treatment; depositing a fourth layer of polysilicon in contact with the third layer of polysilicon said first insulating layer; forming a silicide layer over said fourth polysilicon layer; depositing a second insulating layer over said silicide layer and reflowing said insulator by thermal treatment; opening contact holes through said insulating layers to said silicide layer; and depositing a metal layer into said contact holes to form contacts to said silicide layer to complete formation of said DRAM with capacitor.