Method of making a stacked capacitor dram cell

Claim 1

A process for fabricating a DRAM array on a silicon substrate, said process comprising the following sequence of steps: creating a plurality of separately isolated active areas arranged in parallel interdigitated rows and parallel non-interdigitated columns; creating a gate dielectric layer on top of each active area; depositing a first conductive layer superjacent surface of said array; depositing a first dielectric layer superjacent said first conductive layer; masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over a inner portion of each said active area being separated therefrom by a remnant of said gate dielectric layer; creating of a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line; depositing a second dielectric layer superjacent said array surface; creating a first aligned buried contact location at each said digit line junction in each said active area; depositing a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations; depositing a third dielectric layer superjacent to said second conductive layer; masking and etching said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-like topology; depositing a fourth dielectric layer superjacent said array surface of said waveform-like topology; creating a second aligned buried contact location at each said storage node junction in each said active area, wherein said second aligned buried contact locations are defined by a patterned photomask which exposes a portion of said fourth dielectric layer, said exposed fourth dielectric layer being etched away to expose said storage node junctions; depositing a third conductive layer superjacent said array surface assuming said waveform-like topology in response to existing topology, said third conductive layer making contact to said storage node junctions at said second buried contact locations; patterning said third conductive layer to form a portion of a storage node plate at each said storage node junction, said third conductive layer making contact to said storage node junction at said second buried contact location; isotropically etching a remaining portion of said fourth dielectric layer to thereby expose an underneath portion of said third conductive layer; depositing a fourth conductive layer superjacent said patterning of said third conductive layer and said exposed underneath third conductive layer, and superjacent said array surface assuming said waveform-like topology in response to existing topology, said fourth conductive layer combining with said third conductive layer; patterning and dry etching said fourth conductive layer to form a complete storage node plate and at each storage node junction, said storage node plate having a multi-fingered cross-section; depositing a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent said array surface; and depositing a fifth conductive layer adjacent to and coextensive with said cell dielectric layer to form a cell plate common to the entire memory array.