Stacked surrounding wall capacitor

Claim 1

A process for fabricating a DRAM array on a silicon substrate, said process comprising the steps of: creating a plurality of separately isolated active areas in DRAM array arranged in parallel interdigitated rows and parallel non-interdigitated columns; creating a gate dielectric layer on top of each active area; depositing a first electrically conductive layer superjacent surface of said array; depositing a first dielectric layer superjacent said first conductive layer; masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over an inner portion of each said active area being separated therefrom by a remanent of said gate dielectric layer; creating first and second conductively-doped regions within each said active area, said first and second regions being on opposite side of each said word line, said first region providing digit line junction and said second region providing storage node junction; depositing a second dielectric layer superjacent said array surface; creating a first aligned buried contact location at each said digit line junction in each said active area; depositing a second electrically conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junction at said first buried contact locations; depositing a third dielectric layer superjacent to said second conductive layer; masking and etching said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digit lines running perpendicular to end over said word lines forming a 3-dimensional, waveform-like topology; depositing a first oxide layer superjacent said array surface of said waveform-like topology; creating a second aligned buried contact location at each said storage node junction in each said active area; depositing a third electrically conductive layer superjacent said array surface making contact to said storage node junctions at said second buried contact locations, assuming said waveform-like topology in response to existing topology; depositing a fourth dielectric layer; patterning said third conductive layer and said fourth dielectric layer to form a portion of a storage node plate at each said storage node junction, said storage node plate having a v-shaped cross-section; depositing and patterning a fourth electrically conductive layer, said fourth conductive layer attaching to said third conductive layer thereby forming a completed storage node plate having an elongated v-shaped cross-section; masking said storage node plate with resist and etching away poly stringers present outside a storage node area; removing said resist; isotropically etching said fourth dielectric layer; depositing a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent said array surface; and depositing a fifth electrically conductive layer adjacent to and coextensive with said cell dielectric layer to form a cell plate common to the entire memory array.