Split-polysilicon CMOS DRAM process incorporating selective self-aligned silicidation of conductive regions and nitride blanket protection of N-channel regions during P-channel gate spacer formation

Claim 1

A split-polysilicon process for creating CMOS DRAM circuitry having self-alignedly silicided transistor gates and active areas, on semiconductor material having both N-type material regions and P-type material regions, both types of said regions being covered by a gate dielectric layer, said process comprising the following sequential steps: a) blanket deposition of a first polysilicon layer on top of the gate dielectric layer; b) masking of said first polysilicon layer with a first photomask which, in P-type material regions, defines N-channel gates and interconnects and in N-type material regions, blankets said first polysilicon layer; c) removal of those portions of said first polysilicon layer that are not subjacent the first photomask with a first polysilicon etch; d) stripping of said first photomask; e) self-aligned implantation of a P-type conductivity-creating impurity which functions as a punch-through implant in N-channel active areas; f) blanket deposition of a first principal silicon dioxide spacer layer; g) anisotropically etching the heretofore deposited silicon dioxide in order to create N-channel transistor gate spacers, and to remove all silicon dioxide from N-channel active areas; h) self-aligned, high-dosage implantation of an N-type conductivity-creating impurity to create heavily-doped drain and source regions for N-channel transistors; i) blanket deposition of a first silicon nitride layer; j) blanket deposition of a second polysilicon layer; k) masking of said second polysilicon layer with a second photomask, said second photomask defining a cell plate; 1) removal of those portions of said second polysilicon layer that are not subjacent to the second photomask with a second polysilicon etch to create the cell plate; m) removal of those portions of said first silicon nitride layer that are exposed by said second polysilicon etch; n) blanket deposition of a first anti-silicidation silicon dioxide layer; o) blanket deposition of a protective nitride layer; p) masking of the protective nitride layer with a third photomask that blankets the P-type material regions and defines the P-channel transistor gates and interconnects in the N-type material regions; q) removal of those portions of said protective nitride layer that are not subjacent the third photomask with a second nitride etch; r) anisotropically etching away those portions of the anti-silicidation silicon dioxide layer that were exposed by the second nitride etch; s) anisotropically etching away those portions of the first polysilicon layer that were exposed by etching away portions of the anti-silicidation silicon dioxide layer; t) self-aligned implantation of an N-type conductivity-creating impurity which functions as a punch-through implant in P-channel active areas; u) blanket deposition of a second principal silicon dioxide spacer layer; v) anisotropically etching the heretofore deposited silicon dioxide to create P-channel transistor gate sidewall spacers; w) self-aligned, high-dosage implantation of a P-type conductivity-creating impurity to create heavily-doped source and drain regions for P-channel transistors; x) stripping the protective nitride layer with a third nitride etch; y) blanket deposition of a refractory metal layer; aa) sintering the refractory metal layer in a nitrogen ambient to create a refractory-metal-nitride-covered refractory metal-silicon compound on unoxidized silicon surfaces and refractory metal nitride on all other surfaces; bb) removal of all refractory metal nitride; and cc) annealing the refractory metal-silicon compound to convert it to refractory metal silicide.