Reduced mask manufacture of semiconductor memory devices

Claim 1

Method of forming semiconductor circuit memory devices which include, as a part of each device, a plurality of memory cells and active circuit elements to control signals, the cells and active circuit elements forming a repeating pattern on the device, the method comprising: (a) preparing a silicon wafer and establishing the wafer as a substrate; (b) forming an initial oxide on the wafer; (c) establishing buried contact of rings in the initial oxide; (d) deposit a polysilicon layer on said initial oxide layer and buried contact openings, and patterning said polysilicon layer to simultaneously form gate electrodes and bitlines connected to substrate through the buried contact openings; (e) applying a second oxide layer over the gate electrodes and bitlines; (f) applying a third oxide layer on the second oxide layer; (g) anisotropically etching the second and third oxide layers to form oxide sidewall spacers on the gate electrodes while leaving an oxide layer on top portions of said gate electrodes; (h) forming capacitor plates after said anisotropic etch; (i) forming electrical connections between the various device regions.